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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 23:22:37 +02:00

Fix some problems introduced in commit r948 brought up by carldani

The Intel 28F001BX-T/B chips don't have block locks or mention of
registers; chip is old. The Intel 28F004S5 mentions block locks which
require a remapping registers.

Corresponding to flashrom svn r960.

The Intel 28F004S5 mentions block locks which require a remapping registers.
Fixes problems brought up by carldani because of commit r948.
Signed-off-by: Sean Nelson <audiohacked@gmail.com>
Acked-by: Sean Nelson <audiohacked@gmail.com>
This commit is contained in:
Sean Nelson 2010-03-20 03:01:19 +00:00
parent f63c4364b7
commit fcc4f749f3

View File

@ -2316,7 +2316,6 @@ struct flashchip flashchips[] = {
.model_id = P28F001BXB,
.total_size = 128,
.page_size = 128 * 1024, /* 8k + 2x4k + 112k */
.feature_bits = 0,
.tested = TEST_BAD_WRITE,
.probe = probe_jedec,
.probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */
@ -2331,7 +2330,6 @@ struct flashchip flashchips[] = {
.block_erase = erase_block_82802ab,
},
},
.unlock = unlock_82802ab,
.write = NULL,
.read = read_memmapped,
},
@ -2344,7 +2342,6 @@ struct flashchip flashchips[] = {
.model_id = P28F001BXT,
.total_size = 128,
.page_size = 128 * 1024, /* 112k + 2x4k + 8k */
.feature_bits = 0,
.tested = TEST_BAD_WRITE,
.probe = probe_jedec,
.probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */
@ -2359,7 +2356,6 @@ struct flashchip flashchips[] = {
.block_erase = erase_block_82802ab,
},
},
.unlock = unlock_82802ab,
.write = NULL,
.read = read_memmapped,
},
@ -2372,6 +2368,7 @@ struct flashchip flashchips[] = {
.model_id = E_28F004S5,
.total_size = 512,
.page_size = 256,
.feature_bits = FEATURE_REGISTERMAP,
.tested = TEST_UNTESTED,
.probe = probe_82802ab,
.probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */