As reported by Stefan Tauner on IRC, the new programmer-centric logic
is broken by re-using occupied members of the flashes array when changing
to the next programmer. This fixes it.
patch v2:
prevent probing one chip per programmer even if the array is full. Using
a do-while loop was a bad idea.
Corresponding to flashrom svn r1479.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
These devices have an additional output buffer which is activated only
by pulling ADBUS4 low. This patch was real-life tested with
arm-usb-ocd; arm-usb-ocd-h should be the same (as it shares the same
documentation).
Corresponding to flashrom svn r1478.
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
All chips which use spi_chip_write_256 should be written at native
speed. Chips using spi_chip_write_1 or spi_chip_write_aai will
still be slow.
Thanks to Steven A. Falco for testing with a ST/Numonyx M25P16.
Thanks to David Hendricks for testing with a Winbond W25Q64.
Corresponding to flashrom svn r1477.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Steven A. Falco <sfalco@coincident.com>
Switch from host OS detection to target OS detection.
Complain about unknown target OS/architecture.
Disable annoying format string warnings on DJGPP.
Native and cross-compilation now usually just require setting CC.
Examples:
make CC=i586-pc-msdosdjgpp-gcc
make CC="clang -m64"
make CC=i686-w64-mingw32-gcc
Tested for a boatload of native and cross compilation configurations.
There is a new target "make libpayload" in case you don't want to
specify all tools by hand.
Corresponding to flashrom svn r1476.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: David Hendricks <dhendrix@google.com>
All programmer types (Parallel, SPI, Opaque) now register themselves
into a generic programmer list and probing is now programmer-centric
instead of chip-centric.
Registering multiple SPI/... masters at the same time is now possible
without any problems. Handling multiple flash chips is still unchanged,
but now we have the infrastructure to deal with "dual BIOS" and "one
flash behind southbridge and one flash behind EC" sanely.
A nice side effect is that this patch kills quite a few global variables
and improves the situation for libflashrom.
Hint for developers:
struct {spi,par,opaque}_programmer now have a void *data pointer to
store any additional programmer-specific data, e.g. hardware
configuration info.
Note:
flashrom -f -c FOO -r forced_read.bin
does not work anymore. We have to find an architecturally clean way to
solve this.
Corresponding to flashrom svn r1475.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
All programmer access function prototypes except init have been made
static and moved to the respective file.
A few internal functions in flash chip drivers had chipaddr parameters
which are no longer needed.
The lines touched by flashctx changes have been adjusted to 80 columns
except in header files.
Corresponding to flashrom svn r1474.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Struct flashchip is used only for the flashchips array and for
operations which do not access hardware, e.g. printing a list of
supported flash chips.
struct flashctx (flash context) contains all data available in
struct flashchip, but it also contains runtime information like
mapping addresses. struct flashctx is expected to grow additional
members over time, a prime candidate being programmer info.
struct flashctx contains all of struct flashchip with identical
member layout, but struct flashctx has additional members at the end.
The separation between struct flashchip/flashctx shrinks the memory
requirement of the big flashchips array and allows future extension
of flashctx without having to worry about bloat.
Corresponding to flashrom svn r1473.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Move Asus A8Jm, Asus M6Ne to the laptop section.
No working URL for the A8Jm found.
Corresponding to flashrom svn r1472.
Signed-off-by: Benjamin Bellec <b.bellec@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Push those changes forward where needed to prevent new sign
conversion warnings where possible.
Corresponding to flashrom svn r1470.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The reverse engineering was done by Joshua. The actual patch was
fabricated by Paul with some polishing by Stefan.
Success log:
http://www.flashrom.org/pipermail/flashrom/2011-November/008257.html
Corresponding to flashrom svn r1468.
Signed-off-by: Joshua Roys <roysjosh at gmail.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
The reverse engineering was done by Joshua. The actual patch was
fabricated by Stefan.
Request:
http://www.flashrom.org/pipermail/flashrom/2011-November/008241.html
Success report:
http://paste.flashrom.org/view.php?id=914
Corresponding to flashrom svn r1467.
Signed-off-by: Joshua Roys <roysjosh@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Mugendai <mugendai42@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This looks suspiciously like intel_ich_gpio_set.
Based on that, add board enables for the ASUS P5N-D and P5N-E SLI.
This was tested by Guillaume Poirier-Morency on a P5N-D:
http://www.flashrom.org/pipermail/flashrom/2011-August/007706.html
Corresponding to flashrom svn r1466.
Signed-off-by: Joshua Roys <roysjosh@gmail.com>
Small changes were also contributed and
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Move the serprog specification there and document a few things we could not
figure out on intel platforms yet.
Corresponding to flashrom svn r1465.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
By calling it early ichspi_lock was not set up correctly in accordance
with the corresponding register, hence ich_init_opcodes() was always
trying to programming the opcodes instead of reading them in from the
opmenu in case of a locked down configuration.
Thanks to Jonathan A. Kollasch for reporting this bug.
Corresponding to flashrom svn r1464.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
All programmers are now calling programmer registration functions and
direct manipulations of buses_supported are not needed/possible anymore.
Note: Programmers without parallel/LPC/FWH chip support should not call
register_par_programmer().
Additional fixes:
Set max_rom_decode.parallel for drkaiser.
Remove abuse of programmer_map_flash_region in it85spi.
Annotate several FIXMEs in it85spi.
Corresponding to flashrom svn r1463.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Based on the new opaque programmer framework this patch adds support
for Intel Hardware Sequencing on ICH8 and its successors.
By default (or when setting the ich_spi_mode option to auto)
the module tries to use swseq and only activates hwseq if need be:
- if important opcodes are inaccessible due to lockdown
- if more than one flash chip is attached.
The other options (swseq, hwseq) select the respective mode (if possible).
A general description of Hardware Sequencing can be found in this blog entry:
http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/
Besides adding hwseq this patch also introduces these unrelated changes:
- Fix enable_flash_ich_dc_spi to pass ERROR_FATAL from ich_init_spi.
The whole error handling looks a bit odd to me, so this patch does
change very little. Also, it does not touch the tunnelcreek method,
which should be refactored anyway.
- Add null-pointer guards to find_opcode and find_preop
to matches the other opcode methods better:
curopcodes == NULL has some meaning and is actively used/checked in
other functions.
TODO: adding real documentation when we have a directory for it
Corresponding to flashrom svn r1461.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The type member is enough most of the time to derive the wanted
information, but
- not always (e.g. ich_set_bbar),
- only available after registration, which we want to delay till the
end of init, and
- we really want to distinguish between chipset version-grained
attributes which are not reflected by the registered programmer.
Hence this patch introduces a new static variable which is set up
early by the init functions and allows us to get rid of all "switch
(spi_programmer->type)" in ichspi.c. We reuse the enum introduced
for descriptor mode for the type of the new variable.
Previously magic numbers were passed by chipset_enable wrappers. Now
they use the enumeration items too. To get this working the enum
definition had to be moved to programmer.h.
Another noteworthy detail: previously we have checked for a valid
programmer/ich generation all over the place. I have removed those
checks and added one single check in the init method. Calling any
function of a programmer without executing the init method first, is
undefined behavior.
Corresponding to flashrom svn r1460.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
An opaque programmer does not allow direct flash access and only offers
abstract probe/read/erase/write methods.
Due to that, opaque programmers need their own infrastructure and
registration framework.
Corresponding to flashrom svn r1459.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Changes related to P5GD1 variants:
- Reorder "P5GD1 Pro" in print.c and include a DMI patter to its board enable
- Add an untested "P5GD1(-VM)" board enable and add an entry to print.c
- Add P5GD1-VM/S variant as reported by "Limer"
Changes related to P5GD(2/C) variants:
- Fix the name of "P5GDC-V Deluxe" board enable and add a DMI pattern and
print.c entry. NB: there is no "P5GDC-V" board.
- Add a generic match for P5GD(2/C)* boards with a not tested tag.
This are the potential targets for this according to the asus ftp:
ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/
Unsupported variants of the P5GD2:
P5GD2, P5GD2 Deluxe, P5GD2 Pro, P5GD2-X
(P5GD2 Premium is already tested)
(there seems to be also a P5GD2-TVM/GB/SI in the wild, which is not known to
asus :)
Unsupported variants of the P5GDC:
P5GDC Pro, P5GDC-MX
(P5GDC Deluxe and P5GDC-V Deluxe are already tested)
References:
P5GD1 PRO (dmi "P5GD1 PRO")
smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, *0x814e*
http://www.coreboot.org/pipermail/flashrom/2010-August/004539.html
P5GD1 (dmi "P5GD1")
The non-pro version seems to match the pro pci pattern, but could be
distinguished by the SATA ID of 1043:2604 vs. 1043:2601:
https://launchpadlibrarian.net/62167576/Lspci.txt
or a DMI pattern of course.
P5GD1-VM (dmi "P5GD1-VM")
This does also match the current PCI IDs.
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/465379
- P5GD2 Premium (dmi "P5GD2-Premium")
smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d
http://www.flashrom.org/pipermail/flashrom/2010-August/004555.html
- P5GDC-V Deluxe (dmi "P5GDC-V")
smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d
http://www.flashrom.org/pipermail/flashrom/2010-September/004939.html
- P5GDC Deluxe (dmi "P5GDC")
smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d
http://www.flashrom.org/pipermail/flashrom/2010-September/004684.html
- P5GDC Pro, P5GDC-MX, P5GD2-X, P5GD2 Pro, P5GD2
no useful logs found
- P5GD2-Deluxe (dmi "P5GD2-Deluxe")
smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d
https://bugs.launchpad.net/ubuntu/+source/foomatic-filters/+bug/572514
- P5GD2-TVM/GB/SI (dmi "P5GD2-TVM/GB/SI")
smbus: 0x8086, 0x266a, 0x1043, 0x266a; audio: 0x8086, 0x2668, 0x1043, *0x81a7*
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/462500
Corresponding to flashrom svn r1457.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
and due to the tremendous interest... ;)
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
I disassembled the write enable and the write disable functions from
the Award BIOS image and reconstructed C code to understand for
myself what happens. For details see:
http://www.flashrom.org/pipermail/flashrom/2011-October/008033.html
I compared the download pages of both, abit AV8 and abit AV8-3rd Eye,
and the BIOS downloads are the same. So it's save to assume that this
board enable works on both versions. Tested on AV8.
Corresponding to flashrom svn r1455.
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
http://www.goepel.com/en/jtagboundary-scan/hardware/picotap.html
This device is actually a JTAG adapter, but since it uses standard
FT2232 A interface pins, it can be easily used as SPI programmer
(tested it here successfully). PicoTAP supports only 5V output, so one
needs to reduce this to 3.3V in a same manner as DLP Design DLP-USB1232H, see
http://flashrom.org/FT2232SPI_Programmer#DLP_Design_DLP-USB1232H
for details.
The PicoTAP pin-out is as follows:
PicoTAP | SPI
---------+-------
TCK | SCLK
TMS | CS#
TDI | SO
TDO | SI
/TRST | -
GND | GND
+5V | VCC, HOLD# & WP# after 3.3V regulator
I managed to run PicoTAP in 10MHz, 15MHz and 30MHz modes (by forcing
DIVIDE_BY), against SST25VF016B SPI flash, read/write/erase all worked
fine (write seems somewhat slow).
Corresponding to flashrom svn r1453.
Signed-off-by: Samir Ibradžić <sibradzic@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This was done to ease the review. Another patch will hook up (and
explain) this code later.
Corresponding to flashrom svn r1452.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Thanks to TIAO/DIYGADGET for sponsoring a test device!
This is an FTDI FT2232H based device which provides an easily accessible JTAG,
SPI, I2C, serial breakout. The SPI part can be used to flash SPI flash chips
using flashrom.
http://www.diygadget.com/tiao-usb-multi-protocol-adapter-jtag-spi-i2c-serial.htmlhttp://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User%27s_Manual#SPI_Connector_1
There are two SPI connectors (pin headers) on the board: SPI1, which is
connected to the FT2232H's A interface, and SPI2, which is connected to the
chip's B interface. Both can be used to flash SPI chips:
flashrom -p ft2232_spi:type=tumpa,port=A
flashrom -p ft2232_spi:type=tumpa,port=B
The default interface is A, so for SPI1 you can also just write:
flashrom -p ft2232_spi:type=tumpa
I tested all operations on both interfaces, everything works fine.
Corresponding to flashrom svn r1451.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
- probe_timing was changed to unsigned although we use negative values
for special cases
- some code was not changed along hence did no longer compile:
* dediprog's read and write functions
* linux_spi's read and write functions
- it introduced a number of new sign conversion warnings
(http://paste.flashrom.org/view.php?id=832)
To be safe this patch reverts all changes made in r1448, a corrected
patch will follow later.
Thanks to idwer for pointing out the problem first!
Corresponding to flashrom svn r1450.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Ibex Peak SPI Programming Guide:
The PCH has a mechanism to set up to 5 address ranges from HOST access. These are
defined in PR0, PR1, PR2, PR3 and PR4 in the PCH EDS. These address ranges are NOT
unlocked by assertion of Flash descriptor Override.
Also, the datasheets mention the bit in their description of FRAP but not PR[N].
Corresponding to flashrom svn r1449.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
There is no sign of BBAR (BIOS Base Address Configuration Register)
in the public datasheet (or specification update) of the ICH8. Also,
the offset of that register has changed between ICH7 (SPIBAR + 50h)
and ICH9 (SPIBAR + A0h), so we have no clue if or where it is on
ICH8. Better don't try to touch it at all and assume/hope it is 0.
Corresponding to flashrom svn r1445.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Add headers for the columns and some decoding into human readable format.
Corresponding to flashrom svn r1444.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty
printing of those ICH/PCH flash descriptor sections that are
cached/mapped by the chipset (and which are therefore reachable via
FDOC/FDOD registers).
this includes the following:
- content section:
describes the image and some generic properties (number of
sections, offset of sections, PCH/ICH and MCH/PROC strap
offsets and lengths)
- component section:
identify the different SPI flash chips and their capabilities.
- region section
similarly to a partition table this describes the different regions.
the content of FLREG* is derived from this section.
- master section
defines SPI master (host, ME, GbE) access rights of the
individual regions. the content of PR* is derived from this section.
this is only a part of the data included in the descriptor. other
information can be retrieved from a complete binary dump of the
descriptor region only.
this patch also adds macros and pretty printing for "Vendor Specific
Component Capabilities" registers: there are two of them: lower and
upper. they describe the properties of the address space divided by
FPBA (which allows to use multiple flash chips or partitions with
different properties). the properties of all supported flash chips
(together with their RDIDs) are stored in the same format in table
in a descriptor section (which is used by the ME apparently). a
later patch will use the macros outside of ichspi.c which is the
reason why the prettyprinting function and the register bit macros
are not defined in ichspi.c but ich_descriptors.h (else they would
be moved in the follow-up patch).
because this patch relies on (compiler) implementation-specific
layouting of bit-fields, it checks for correct layout before taking
any action on runtime.
Corresponding to flashrom svn r1443.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Adds a new opcode (0x13) that just relays SPI bytes and wires it up to be
usable within serprog.c. Checks for mandatory opcodes are moved around and
changed a bit, but non-SPI programmers should not be harmed by this patch.
Corresponding to flashrom svn r1442.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- add voltage ranges
- center some headers (test values OK, No, ? are centered via wiki templates)
- fix style error in header (align:right -> text-align:right)
Corresponding to flashrom svn r1441.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Telling the user to use "force_I_want_a_brick" if it is not even a
laptop, is a bit over-the-top. Introduce a new laptop parameter
"this_is_not_a_laptop" that allows to force operation, but only if
the detection is not sure.
Corresponding to flashrom svn r1440.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Write and erase are NOT yet supported!
Probe and read are tested by Andrew Morgan and Uwe Hermann on Intel NICs.
Corresponding to flashrom svn r1439.
Signed-off-by: Andrew Morgan <ziltro@ziltro.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Besides adding output for the voltage ranges, this patch also changes
various aspects of the -L output:
- sizes are right aligned now with a fixed length of 5
- space between columns is selectable with a constant
- test results are always shown in the same column ("PR" and " R"
instead of "PR" and "R ")
- vendor and device names are split on a delimiter (currently '/') and
spread over mutliple lines but only if the tokens are not too short.
all other columns are printed on the first line of a chip.
- voltage ranges are printed in verbose mode only
it also gets rid of POS_PRINT and digits
Corresponding to flashrom svn r1438.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The rayer_spi driver defaults to the RayeR cable, but selecting other
predefined pin layouts with the type= parameter is possible:
flashrom -p rayer_spi:type=xilinx
Corresponding to flashrom svn r1437.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This allows easier identification of the flash chip used in verbose logs.
There is no (additional) output if
* -c is used to specify a flash chip, or
* multiple chips are detected, or
* no chips are detected.
Corresponding to flashrom svn r1436.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- introduce a new variable 'wanted' that is used instead of 'new'
- use 'new' for the actual value contained in BIOS_CNTL after we tried to write it
- rephrase the warning which now also includes the old and new values besides the wanted one
Corresponding to flashrom svn r1435.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
The chip code is untested, only one erase function out of two is currently
implemented, and unlocking/printlocking is not yet supported.
Thanks Mattias Mattsson <vitplister@gmail.com> for the initial patch!
Corresponding to flashrom svn r1434.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Bugfix: Do not accept multiple conflicting --programmer selections.
Restriction: Do not accept multiple --programmer selections even if
there is no conflict.
Unexport the programmer variable.
programmer_init requires the programmer as first parameter.
The default programmer selection is now part of cli_classic.
Corresponding to flashrom svn r1433.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Intel's Tunnel Creek chipset supports both an SPI and an LPC bus. Set the
chipset table entry for Tunnel Creek to the new function
enable_flash_tunnelcreek(), which will read the hardware straps and return
support for the bus that has been used for booting. This function uses
ich_init_spi() with ich_generation set to 7 for initializing the SPI bus
if necessary.
SPI functionality tested on actual hardware, Tunnel Creek LPC interface not
tested yet (missing hardware for that).
Log file / success report:
http://www.flashrom.org/pipermail/flashrom/2011-September/007823.html
Corresponding to flashrom svn r1430.
Signed-off-by: Ingo Feldschmid <ifel@msc-ge.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
