SPI bitbanging on devices which speak SPI natively has a dual-use
problem: We need to shut down normal SPI operations to do the bitbanging
ourselves. Once we're done, it makes a lot of sense to reenable "normal"
SPI operations again. Add request_bus/release_bus functions to struct
bitbang_spi_master.
Add a bitbang shutdown function (not used yet).
Change MCP SPI and Intel NIC SPI to use the new request/release bus
infrastructure.
Cosmetic changes to a few error messages (80 column limit).
There are multiple possible strategies for bus request/release:
- Request at the start of a SPI command, release immediately afterwards.
- Request at the start of a SPI multicommand, release once all commands
of the multicommand are done.
- Request on programmer init, release on shutdown.
Each strategy has its own advantages. For now, we will stay with the
first strategy which worked fine so far.
Corresponding to flashrom svn r1171.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Tested on a 82541PI (0x8086, 0x107c) using 32-bit hardware.
The last line in nicintel_request_spibus() could be changed so that FL_BUSY
is used instead.
Shortened sample log:
[...]
Found "Intel 82541PI Gigabit Ethernet Controller" (8086:107c, BDF 01:03.0).
Found chip "ST M25P10.RES" (128 KB, SPI) at physical address 0xfffe0000.
Multiple flash chips were detected: M25P05.RES M25P10.RES
Please specify which chip to use with the -c <chipname> option.
[...]
Corresponding to flashrom svn r1151.
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
