Per report from Mario Rogen. Thanks!
Corresponding to flashrom svn r341 and coreboot v2 svn r3736.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
This has been confirmed by Stéphan Guilloux.
Corresponding to flashrom svn r340 and coreboot v2 svn r3731.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This helps a lot if we have to track down configuration weirdnesses.
Corresponding to flashrom svn r338 and coreboot v2 svn r3723.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Not all chips support all commands, so allow the implementer to select
the matching function. Fix a layering violation in ICH SPI code to be
less bad. Still not perfect, but the new code is shorter, more generic
and architecturally more sound.
TODO (in a separate patch): - move the generic sector erase code to
spi.c - decide which erase command to use based on info about the chip -
create a generic spi_erase_all_sectors function which calls the generic
sector erase function
Thanks to Stefan for reviewing and commenting.
Corresponding to flashrom svn r337 and coreboot v2 svn r3722.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
This is slightly slower (ha, ha), but works on boards with a locked
opmenu. Tested on ICH7 and works.
Corresponding to flashrom svn r336 and coreboot v2 svn r3721.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
- SST SST39SF010A
- Winbond W29C011
Tested by me on actual hardware, all operations.
Corresponding to flashrom svn r334 and coreboot v2 svn r3708.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Using block erase d8 as discussed with Peter Stuge
Corresponding to flashrom svn r333 and coreboot v2 svn r3707.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Corresponding to flashrom svn r332 and coreboot v2 svn r3706.
Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
Acked-by: Ed Swierk <eswierk@aristanetworks.com>
Tested by Martin Stecklum <stecky@gmx.net> (both write and erase).
The tests were done on an MSI MS-7065 board, so that's supported now too.
Corresponding to flashrom svn r331 and coreboot v2 svn r3697.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Untested, but should work just as well as the other *PIIX* southbridges
according to the datasheets.
Corresponding to flashrom svn r330 and coreboot v2 svn r3696.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This has been tested on hardware by me.
Corresponding to flashrom svn r327 and coreboot v2 svn r3682.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Corresponding to flashrom svn r326 and coreboot v2 svn r3669.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Based on the 5595 datasheet and uniflash 1.40 sources, only looking for info
about SiS620.
Corresponding to flashrom svn r325 and coreboot v2 svn r3668.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
It is not possible to write enable that area once the register is set so
print a warning.
Corresponding to flashrom svn r324 and coreboot v2 svn r3659.
Signed-off-by: Marc Jones <marcj.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The ICH9 and ICH10 data sheets are identical regarding FWH/SPI flash
interfaces, so this just adds the required PCI IDs.
Corresponding to flashrom svn r323 and coreboot v2 svn r3648.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
Fully tested on AM29F002NBT.
Probing, reading, and erasing use the Jedec-routines, whereas writing
resort to the recent write_en29f002a(), since also these chips use a
byte wise algorithm.
Corresponding to flashrom svn r321 and coreboot v2 svn r3639.
Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
It replaces the write function to one based on write_byte_program_jedec()
instead of write_page_write_jedec(), as this part does not support page
programming.
I have verified the NT variant to fully work now, and adjusted the test
status accordingly. The N variant *should* also work with this patch, but
remains untested.
Corresponding to flashrom svn r320 and coreboot v2 svn r3619.
Signed-off-by: Tim ter Laak <timl@scintilla.utwente.nl>
Acked-by: Peter Stuge <peter@stuge.se>
Per report from Daniel Lindenaar. Thanks!
Corresponding to flashrom svn r319 and coreboot v2 svn r3618.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
All operations tested by me on hardware.
Corresponding to flashrom svn r317 and coreboot v2 svn r3615.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Fully tested for Probe/Read/Erase/Write on EN29F002NT.
Jedec subroutines 'probe_jedec()' and 'erase_chip_jedec()'
are still in use, but a tailored 'write_en29f002a()' is
needed due to a byte wise writing mechanism for this chip.
Corresponding to flashrom svn r316 and coreboot v2 svn r3602.
Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Per report from Kevin O'Connor. Thanks Kevin!
Corresponding to flashrom svn r315 and coreboot v2 svn r3570.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
This removes the false positive matches we've been seeing, and also removes
the true positive match in case there is more than one flash chip and the 2nd
or 3rd are unknown - but I think that case is uncommon enough to warrant the
improvement in the common case. Use flashrom -frc forced read if you have the
uncommon case, and/or please add the flash chip to the flashchips array.
Corresponding to flashrom svn r313 and coreboot v2 svn r3562.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Per test report from Bari Ari. Thanks!
Corresponding to flashrom svn r312 and coreboot v2 svn r3557.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Per test report from Ward.
Corresponding to flashrom svn r311 and coreboot v2 svn r3541.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
The KT4V is autodetected and supports the KT3 Ultra 2 with "-m msi:kt4v"
(but is not autodetected, yet).
Corresponding to flashrom svn r309 and coreboot v2 svn r3528.
Signed-off-by: Sean Nelson <snelson@nmt.edu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Don't calculate "flash_baseaddr" until the final value of "size"
is known, otherwise we end up trying to map a page right after
the end of memory.
Fixes#112.
Corresponding to flashrom svn r308 and coreboot v2 svn r3502.
Signed-off-by: Segher Boessenkool <segher@kernel.crashing.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Per test report from Marcel Konrad. Thanks!
Corresponding to flashrom svn r307 and coreboot v2 svn r3485.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Corresponding to flashrom svn r306 and coreboot v2 svn r3464.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Corresponding to flashrom svn r305 and coreboot v2 svn r3462.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
W39V040C does standard JEDEC commands except chip erase so add a small driver.
probe_w39v040c() prints the block lock pin status when a chip is found.
The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs.
Many thanks to Daniel McLellan for testing all of this on hardware!
Build tested by Uwe.
Corresponding to flashrom svn r304 and coreboot v2 svn r3431.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
While writing a new SPI driver I fixed some things in the SPI code:
All calls to spi_command() had unneccessary #define duplications, and in some
cases the read count define could theoretically become harmful because NULL was
passed for the read buffer. Avoid a crash, should someone change the #defines.
I also noticed that the only caller of spi_page_program() was the it87 driver,
and spi_page_program() could only call back into the it87 driver. Removed the
function for easier-to-follow code and made it8716f_spi_page_program() static.
The ichspi driver's static page functions are already static.
Corresponding to flashrom svn r302 and coreboot v2 svn r3418.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Flash.h is a database of known IDs, whereas flashchips.c is a database
of chips for which support has been implemented. Keep it that way.
Corresponding to flashrom svn r300 and coreboot v2 svn r3416.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This patch adds support to the AMIC A29002 chip in its top and bottom
configuration to flashrom. Additionally, the alphabetic order of the
AMIC chips was fixed.
The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>.
A29002T PREW functionality was tested and works.
This flash chip has asymmetric sector layout so it is important to use the
mx29f002 driver, which does chip erase before writing, rather than am29f040b,
which uses sector erase.
Corresponding to flashrom svn r299 and coreboot v2 svn r3415.
Signed-off-by: Andreas Thienemann <andreas@bawue.net>
Acked-by: Peter Stuge <peter@stuge.se>
Corresponding to flashrom svn r298 and coreboot v2 svn r3414.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Uses the 0.0 Host bridge CN700/VN800/P4M800CE/Pro and 11.0 ISA bridge devices
with their 1106:aa08 subsystem id:s for autodetection.
Corresponding to flashrom svn r297 and coreboot v2 svn r3413.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Make stuff fit in 80 chars/line etc.
Corresponding to flashrom svn r296 and coreboot v2 svn r3412.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Thanks to Paul Seidler and Ward Vandewege for testing.
Corresponding to flashrom svn r295 and coreboot v2 svn r3411.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Corresponding to flashrom svn r294 and coreboot v2 svn r3410.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Per test report from Björn Gerhart. Thanks!
Corresponding to flashrom svn r293 and coreboot v2 svn r3409.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
It's not absolutely perfect, but the likelihood of this check to fail is
0.000000000000000000000000013 (1.3*10^-26) which is good enough for me.
Corresponding to flashrom svn r292 and coreboot v2 svn r3408.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
