Corresponding to flashrom svn r291 and coreboot v2 svn r3407.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
I'm am flashing this chip several times a day. Also enable unlocking
which is only needed when running coreboot, that slipped in the original
commit and through the original review ;-) So it must be trivial enough.
Corresponding to flashrom svn r290 and coreboot v2 svn r3406.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Thanks to Jake for the test report!
Corresponding to flashrom svn r289 and coreboot v2 svn r3405.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Thanks to Stefan for pointing this one out.
Corresponding to flashrom svn r287 and coreboot v2 svn r3403.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Needed at least for GIGABYTE:m57sli in coreboot to match gigabyte:m57sli in
flashrom.
Corresponding to flashrom svn r286 and coreboot v2 svn r3402.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
At some point the flash bus will be part of struct flashchip.
Pardon me for pushing this in, but I think it is important to beware of further
decay and it will improve things for other developers in the short run.
Carl-Daniel, I will consider your suggestions in another patch. I want to keep
things from getting too much for now. The patch includes Rudolf's VIA SPI
changes though.
Corresponding to flashrom svn r285 and coreboot v2 svn r3401.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This enables to use the new probing code.
Corresponding to flashrom svn r284 and coreboot v2 svn r3400.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
Following patch adds support for that.
Corresponding to flashrom svn r283 and coreboot v2 svn r3399.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
It is similar with few documented exceptions to ICH7 SPI controller.
Corresponding to flashrom svn r282 and coreboot v2 svn r3398.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back
to 0 when BOOT BIOS Straps indicate something else than SPI.
Also fixes a build error in ichspi.c with gcc 4.2.2.
Corresponding to flashrom svn r280 and coreboot v2 svn r3395.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* ICH7 SPI support
* fix some variable names in ichspi.c (Offset -> offset)
* Dump ICH7 SPI bar with -V
* Improve error message in case IOPL goes wrong. (It might not even be an IOPL)
Corresponding to flashrom svn r278 and coreboot v2 svn r3393.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Corresponding to flashrom svn r277 and coreboot v2 svn r3392.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Per test report from Alex Perez. Thanks Alex!
Corresponding to flashrom svn r275 and coreboot v2 svn r3389.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Per test report from Andrew Paprocki. Thanks Andrew!
Corresponding to flashrom svn r274 and coreboot v2 svn r3388.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
We should follow data sheet timing, even if chips have been tested to answer
faster in the field.
Corresponding to flashrom svn r273 and coreboot v2 svn r3387.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Preparation for a probe optimization patch. This patch does not change any
functionality. spi_probe_rdid was tested to still work on my M57SLI rev 2.
The idea is to have error checks return error immediately when something
fails, rather than having code inside an if block where the condition
tests for success.
This means: Less indentation, more clear what the code is checking.
Corresponding to flashrom svn r272 and coreboot v2 svn r3386.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
Corresponding to flashrom svn r271 and coreboot v2 svn r3385.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
DOC support has been disabled by default for many years. The write function
does nothing but print text. It has a call to write_page_md2802() commented
out, but that function does not exist. This is dead code with ugly #ifdefs.
Updates README to reflect that there was a time when there was code, but it
didn't work. Removes M-Systems #defines and also includes svn rm msys_doc.*
Corresponding to flashrom svn r269 and coreboot v2 svn r3382.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Many thanks to Julio Cesar Costa for the test report!
Corresponding to flashrom svn r268 and coreboot v2 svn r3379.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Thanks to Urja Rannikko for reporting test results with these flash chips.
Corresponding to flashrom svn r263 and coreboot v2 svn r3374.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Run time is increased a few 100ms but this is needed for reliability.
I consider this trivial.
Corresponding to flashrom svn r262 and coreboot v2 svn r3373.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Jens sent the first patch that added A49LF040A to flash.h and flashchips.c
using _jedec and _49lf040 functions.
An issue was found with probe_w29ee011() for the Winbond W29EE011, which
caused the A49LF040A to no longer respond to any commands.
Ward made a patch to disable probing by default for the W29EE011 following
some discussion. Using -c W29EE011 will make flashrom probe for the chip.
Peter did some more datasheet diving and found that the Pm49FL00x functions
suited this chip quite well because of the block locking registers in
A49LF040A, and finally tested PROBE READ ERASE WRITE to work on ALIX.3c3.
Ward confirmed that this works on alix.2c3 too.
Corresponding to flashrom svn r260 and coreboot v2 svn r3368.
Signed-off-by: Jens Kuehnel <coreboot@jens.kuehnel.org>
Signed-off-by: Ward Vandewege <ward@gnu.org>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
When flash chip detection fails, it is still useful and possible to read the
flash chip contents. If no flash chip is found in normal probes and the
-f -r -c CHIPNAME options are given, a successful probe for the specified
chip is forced, and then flashrom reads the flash chip using either the read
function for the specified chip, or if there is none, a simple memcpy().
The patch also moves the global variable int force in flashrom.c into main()
and passes it as a parameter to layout.c:show_id(), which was the only other
function that used the variable. This is needed to avoid confusion with the
new parameter int force which is added to flashrom.c:probe_flash() and used
to force probe success for the chip named in char *chip_to_probe.
Corresponding to flashrom svn r259 and coreboot v2 svn r3367.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
Uses the VT8237 ISA bridge with mainboard subsystem ID and Realtek 8139 with
mainboard subsystem ID for board detection.
Corresponding to flashrom svn r258 and coreboot v2 svn r3366.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com>
Thanks to Reinder for clean room reverse engineering and data sheet diving!
This board is autodetected because there are some good BioStar subsystem IDs.
Matching uses onboard VT6420 SATA RAID with subsystem BioStar 3206 and
onboard UniChrome Pro IGP graphics with subsystem BioStar 1202.
Corresponding to flashrom svn r256 and coreboot v2 svn r3364.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com>
SST SST49LF160C is confirmed to work for PROBE READ ERASE WRITE, at least on
2 MCP55-based boards (gigabyte m57sli v1 and supermicro h8dmr).
On the m57sli board, it only works > 512K when booted into coreboot; the
proprietary bios seems to do something weird where it locks rom access down
to the first 512K of the chip.
Corresponding to flashrom svn r255 and coreboot v2 svn r3360.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Corresponding to flashrom svn r254 and coreboot v2 svn r3358.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Corresponding to flashrom svn r253 and coreboot v2 svn r3357.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
I have tested MX25L4005, S25FL016A and W39V080A myself.
Thanks also to the following testers:
SST49LF008A Bernhard M. Wiedemann
W39V040B Dan Lenski
Corresponding to flashrom svn r252 and coreboot v2 svn r3356.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
Tested by me on actual hardware (all operations) - Artec Group DBE62
with SST 49LF004B
Corresponding to flashrom svn r251 and coreboot v2 svn r3350.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
- AMD Am29F040B
- SST SST39SF020A
- Winbond W29C020C
- Winbond W29EE011
- Winbond W49F002U
All of them tested by me on actual hardware (all operations).
Corresponding to flashrom svn r250 and coreboot v2 svn r3349.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- Fix typos and inconsistencies.
- Drop duplicate line which tells us the chip name twice.
- Also print the chip vendor, not only the name.
Corresponding to flashrom svn r249 and coreboot v2 svn r3348.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Corresponding to flashrom svn r248 and coreboot v2 svn r3347.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Tested on actual hardware.
This patch add an ich_gpio_raise() function which can be re-used by other
board-specific funtions which need to raise GPIOs on ICHx southbridges.
This also fixes bug #7, see http://tracker.coreboot.org/trac/coreboot/ticket/7,
as it turned out the ICH2 (and other ICHx) code works fine.
Corresponding to flashrom svn r247 and coreboot v2 svn r3346.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Corresponding to flashrom svn r246 and coreboot v2 svn r3345.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This patch addresses different argument order of outX() calls,
FreeBSD-specific headers, difference in certain type names and system
interface names, and also FreeBSD-specific way of gaining IO port
access.
Corresponding to flashrom svn r245 and coreboot v2 svn r3344.
Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The PMC chips understand both LPC and FWH flash commands. When in FWH mode
(MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block
Locking Registers by default lock the flash chip for write and erase - in
addition to any chipset write protection.
This patch adds unlock operations before Pm49FL004/2 write and erase, and
it includes an svn mv pm49fl004.c pm49fl00x.c
Thanks go to Nikolay for this patch.
Corresponding to flashrom svn r243 and coreboot v2 svn r3332.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Bari Ari <bari@onelabs.com>
It was a straight cut'n'paste from SST 28SF040 code and the person doing
the cut'n'paste didn't even bother to check the data sheet. The SST
39SF020 is completely incompatible with the 28SF040.
No need for replacement. According to the data sheet, standard JEDEC
commands will work and we have those commands in the tree already.
Corresponding to flashrom svn r242 and coreboot v2 svn r3331.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@settoplinux.org>
