Support for the Intel C620 Series Chipset SPI Controller (rev 04) is added
to enable SPI flash access on the following platform:
- Intel Xeon D-2187NT
Support for this controller was shortly tested on the platform above.
The flash is recognized, some regions of the flash are locked.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Tested-by: Jakov Petrina <jakov.petrina@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1
Reviewed-on: https://review.coreboot.org/c/flashrom/+/44162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The parsing of the output of archtest.c produced an unexpected
value on AArch64 NixOS. For example, the make variable ARCH was set to:
```
bit outside of fd_set selected
arm
```
This made the arch and OS checks fail.
This commit simplifies the parsing, making it more robust.
The C files archtest.c, endiantest.c and os.h used to set the
TARGET_OS, ARCH and ENDIAN variables, respectively, output
the result of the test as the final line, so just extracting
the final line and removing double quoting is enough.
This commit also fixes a bug with debug_shell lacking escaping
single quotes, which prevented using the single quote in the
debug_shell calls. It used to work by accident before this fix;
the line in the call happened to contain a balanced pair of double
quotes and lacked other characters that needed escaping, which
didn't break the debug_shell, but this was accidental and very
brittle.
Signed-off-by: Pyry Kontio <pyry.kontio@drasa.eu>
Change-Id: Iaa4477a71e758cf9ecad2c22f3b77bc6508a3510
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
W25Q256JW currently has two variants, the W25Q256JW with device
ID 0x6019 added in commit be4682d and the W25Q256JW_DTR (aka
W25Q256JW-IM) with device ID 0x8019 added by this patch.
Winbond W25Q256-series chips have a few device IDs:
0x4019: W25Q256FV
0x6019: W25Q256JW
0x7019: W25Q256JV
0x8019: W25Q256JW_DTR
Hence we need to be more specific with naming than usual to avoid a
false positive with wildcards.
Change-Id: I50a6de2c915f9201c458378fcc49130ead73d8c4
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/42386
Reviewed-by: Simon Buhrow
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This enables the -o option which is used to collect logs for debugging.
Change-Id: If6c12c682ba72cd519e30f1f8c96552322ff75e3
Signed-off-by: Richard Hughes <richard@hughsie.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/42230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add missing line ends, and add a note about the first version of the
updater which contains the necessary V3 bridge feature.
Change-Id: Ib45efa37b192489bdfe26f1f0fd1d81035a08c70
Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43900
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds support for the Winbond W25X05CL SPI flash chip. The
Winbond W25X05CL is a 512Kib (64 KiB) SPI flash chip with 4KiB sectors.
I have tested this patch with a Bus Pirate (v3b) and an in-circuit W25X05CL
flash chip using a test clip. Reading, erasing, and writing all function
as expected.
Change-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc
Signed-off-by: Jacob Appelbaum <jacob@appelbaum.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43573
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
fileno requires _POSIX_C_SOURCE to only be defined.
nanosleep requires _POSIX_C_SOURCE to be defined to 199309L.
strndup requires _POSIX_C_SOURCE to be defined to 200809L.
Change-Id: Idb80937bb78e173eb03f2a0c0cdd8925fcd7bfa1
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Without this, `gcc -E endiantest.c` can fail and return the incorrect
endiannes as well as exiting with non-zero. Here is the actual error
shown in the output:
endiantest.c:2:31: error: #if with no expression
#if __FLASHROM_LITTLE_ENDIAN__
I was able to reproduce this using gcc-6.3.0 and clang-4.0.1, but
newer compilers didn't have this issue.
Change-Id: Iba2febd861471ec821a494336e800c2564984332
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
GSC firmware asserts EC_RST_L before programming the AP with
raiden_debug:target=AP.Some Chromium devices don't power the AP flash
when the EC is in reset. These boards can't flash the AP with the
current CCD behavior. This change adds a custom_rst raiden_debug param
to tell Cr50 not to assert EC_RST_L or touch any reset signals while
flashing the AP. Users will need to configure the reset signals before
running the flashrom command.
BUG=b:154885210
BRANCH=none
TEST=manual
flashrom -p raiden_debug:target=EC -r ec.bin
flashrom -p raiden_debug:target=AP -r ap.bin
flashrom -p raiden_debug:target=AP,custom_rst=true -r ap.bin
flashrom -p raiden_debug:target=AP,custom_rst=inv -r ap.bin
flashrom -p raiden_debug -r base.bin
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Change-Id: I2da26469120c5304bc129b5578fcb7ca805fc1d1
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43527
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for the USB SPI V2 protocol and its documentation.
The protocol version number uses the bInterfaceProtocol field in
USB to identify which device to use, this enables us to support
both V1 and V2 with the same host.
The USB SPI V2 protocol adds the ability to perform multi-packet
USB SPI transfers. This results in fewer USB messages exchanged,
larger SPI transfers, and faster flashing speeds.
BUG=b:139058552
BRANCH=none
TEST=Manual testing of ServoMicro and Flashrom when performing
reads, writes, and verification of the EC firmware on Nami
with a USB SPI V1 protocol device
TEST=Manual testing of ServoMicro and Flashrom when performing
reads, writes, and verification of the EC firmware on Nami
with a USB SPI V2 protocol device
TEST=Builds
Signed-off-by: Brian J. Nemec <bnemec@chromium.com>
Change-Id: Ie356c63b521c0cc11a4946ffac128ec7139f0bec
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41533
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a configuration stage to the initialization. This enables
us to dynamically set the maximum SPI write and read limits
based on the device we are connected to and switch the command
function. These changes will enable us to have larger SPI
transfers in protocol V2 and separate out the logic flow used
for the different protocols.
BUG=b:139058552
BRANCH=none
TEST=Manual testing of ServoMicro and Flashrom when performing
reads, writes, and verification of the EC firmware on Nami.
TEST=Builds
Signed-off-by: Brian J. Nemec <bnemec@chromium.com>
Change-Id: Id404af14e55fa0884e29f28880206aaad4deba66
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41532
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add context states to handle the USB packets, these allow us to
simplify the process of loading data from the transmit buffer
into a USB packets' data section and from a USB packet to it's
receive buffers. These will also keep track of the size of the USB
packet allowing a simpler interface to transmit them.
Helper functions have been added to help with copying data between
the transmit and receive context states to and from the USB packets.
BUG=b:139058552
BRANCH=none
TEST=Manual testing of ServoMicro and Flashrom when performing
reads, writes, and verification of the EC firmware on Nami.
TEST=Builds
Signed-off-by: Brian J. Nemec <bnemec@chromium.com>
Change-Id: Id7b598b39923b4b8c1b6905e5d5c5a2be4078f96
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Add context states to handle the read and write buffers as transmit
and receive states. These are used to keep track of the number of
bytes transmitted and received allowing future support of multi-packet
messages in the v2 protocol and easier integration with a unified USB
packet context.
BUG=b:139058552
BRANCH=none
TEST=Manual testing of ServoMicro and Flashrom when performing
reads, writes, and verification of the EC firmware on Nami.
TEST=Builds
Signed-off-by: Brian J. Nemec <bnemec@chromium.com>
Change-Id: Ic6eea82ffc604ec56278f7aaa0deafe0cf75973c
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41608
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Perform some clean up the USB SPI protocol 1 prior to adding
protocol 2 to improve consistency and correct minor issues.
* Minor clean up the comments descriptor for the protocol.
This adds the location of another relevant file, corrects the
omission of one of the protocol modes, makes the direction
of the packets explicit, and minor formatting changes.
* Fix typos in constants associated with the retry mechanism.
* Clean declarations to match the EC code formats.
* Updates the error message formatting so protocol V1 closely
matches the V2 protocol for consistency.
* Minor changes to the structure, moving validation of the
arguments earlier in the transfer. Overall to keep V1 and
V2 closer aligned and reduce future changes in the V1 code.
BUG=b:139058552
BRANCH=none
TEST=Builds
Signed-off-by: Brian J. Nemec <bnemec@chromium.com>
Change-Id: I17e62dabee2724eecf8d5a1a7827f06f0c7514df
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41597
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename the structures from the USB SPI which are specific
to the V1 protocol.
BUG=b:139058552
BRANCH=none
TEST=Builds
Signed-off-by: Brian J. Nemec <bnemec@chromium.com>
Change-Id: I70b43af50d872d850dae287d99bcd768107a1cad
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The ich_init_spi() function takes spibar as a parameter
and sets the global ich_spibar with it but then uses the
global symbol instead of using the parameter directly.
Change-Id: Id809c33d8a4074acbee8e1cd8e3b7b00ce0cb3ec
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Make the two prettyprint functions pure by taking the
ich_generation value as a function parameter over a global
variable:
* prettyprint_ich9_reg_hsfs()
* prettyprint_ich9_reg_hsfc()
Change-Id: I5d4fb012c6b9b843ac30c1fe2ea6fe754c545a43
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43501
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Work towards dropping ich_generation global usage and make
the ich_set_bbar() function pure.
Change-Id: I6da6dccb413cbafa2fbaca213574f22c7a258139
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Work towards dropping ich_generation global usage and make
the ich_init_opcodes() function pure.
Change-Id: I68cc078cc8bc1c772f52ca3e5e12559991180210
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Work towards dropping ich_generation global usage and make
the ich_init_spi() function more pure.
Change-Id: I5293e7ae6f20a2299577172655c2926861091f5a
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This fixes a regression with the Fedora package.
Change-Id: I881bd5002a842072ce9dadea033c51a2668f9e7c
Signed-off-by: Richard Hughes <richard@hughsie.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38939
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
File read/write semantics are different between POSIX and Windows. In
particular Windows file read/write functions return a boolean type to
indicate success or failure, while the POSIX equivalents return a
signed integer indicating number of bytes read if successful or -1 if
not.
This attempts to correct some error handling paths for Windows and
avoid invalid comparisons that were causing compilation issues.
Reported on https://github.com/flashrom/flashrom/issues/149
Change-Id: Ib179d51ede2dbd38f54f3641bfe90340a6a87e31
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43051
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's not used anywhere, but it should be correct if we continue to
keep it in.
Change-Id: I8a6941c2906dda2c5aac5e0af3364fd2ac5773f3
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/42763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Nicklas Lennert wrote me via the flashrom mailing list that
he successfully ran read, write and verify cmd.
Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de>
Change-Id: I3608945a38b5ed42b8b2b9b2b388cdea97141d7b
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This adds the CMocka unit-testing infrastructure into
the meson build system which we will latter follow up
with unit-tests for flashrom's core logic.
BUG=b:157280555
BRANCH=none
TEST=builds
Change-Id: I66665f56627b3d99049176bfbebbd771b080370a
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It was indented with two spaces instead of one tab. Fix it.
Change-Id: I18051ae4433b267b9552a034a67d7830b9206c20
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
With this change flashrom can detect, enable and flash on this board
both under vendor BIOS and coreboot.
Change-Id: I395ff50fbcda8ecdaa26033f0d99b2b0eb42f7ff
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When hardware write protect is applied, flashrom crashed and
generate coredump. spi_disable_blockprotect_generic() calls
flash->chip->printlock() method when disable was failed,
but this method is optional, can be NULL depends on type of
flashrom chip. NULL pointer check before call is added to
avoid crash.
BRANCH=none
BUG=b:129083894
TEST=Run on Mistral P2
(On CR50 console, run "wp disable")
flashrom --wp-range 0 0x400000
flashrom --wp-enable
(On CR50 console, run "wp enable")
flashrom -r /tmp/test.bin
Verify "Block protection could not be disabled!" is shown,
but flash read completes.
Signed-off-by: Yuji Sasaki <sasakiy@chromium.org>
Change-Id: I81094ab5f16a85871fc9869a2e285eddbbbdec4e
Reviewed-on: https://chromium-review.googlesource.com/1535140
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: SANTHOSH JANARDHANA HASSAN <sahassan@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40468
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enables the USB SPI transfer retry mechanism when the error code
USB_SPI_WRITE_COUNT_INVALID is returned. This error code can
indicate a recoverable USB transfer failure.
BUG=b:153887087
BRANCH=none
TEST=Manual testing of ServoMicro and Flashrom when performing
reads, writes, and verification of the EC firmware on Nami.
TEST=Modified ServoMicro to randomly corrupt USB packets when
reading the packet length to replicate bad packets and the
verify recovery is successful.
Change-Id: I9e6b2ccec0b06aab0d6920f1bddf108058e5d6b1
Signed-off-by: Brian J. Nemec <bnemec@chromium.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41152
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turns out the MST likely doesn't need these so-called defaults
to be written for the purposes of spi flashing.
BUG=b:152558985,b:148745673
BRANCH=none
TEST=builds
Change-Id: Ieb938cf0805b22692d61db23795208c9be962b60
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Chip erasures take much longer than sector and bank
erasures. Allow the wait loop helper to multiply the
max timeout in this very specific case while quickly
timeout for other ops that are expected to be shorter.
V.2: Fix nonsense fall though warn-err
BUG=b:152558985,b:148745673
BRANCH=none
TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E &&
flashrom -p realtek_mst_i2c_spi:bus=8 -w foo
(cycle)..
Change-Id: I4a36aa3101827e69eb244775d25bbb476d4bb780
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Turns out broken erasures highlighted some of the issues
in the write256 implementation. After a fair amount of
time deciphering scarce documentation details a correct
implementation was finally derived.
V.2: Rename 'start_program() -> execute_write()' to
clarify the intention and not to overload the term
'program' since the MST actually runs a 'program'
itself.
BUG=b:152558985,b:148745673
BRANCH=none
TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E &&
flashrom -p realtek_mst_i2c_spi:bus=8 -w foo &&
flashrom -p realtek_mst_i2c_spi:bus=8 -r foo &&
hexdump -C foo
Change-Id: If61ff95697f886d3301a907b76283322c39ef5c7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Before issuing SPI opcodes into 0x61 the top three BITS of
0x60 need to be carefully crafted. Correctly craft these
in the case of SPI erasures and document this registers
expectations. Clean up remaining debug comments while we
are here.
BUG=b:152558985,b:148745673
BRANCH=none
TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E &&
flashrom -p realtek_mst_i2c_spi:bus=8 -r foo &&
hexdump -C foo
Change-Id: Ib11ba8f63b11a1c5ebaa68deb7971648de8c2ecd
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/41079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
If the transfer failed, the data might be invalid.
Change-Id: I3ad9daa00a54e2a3954983cec91b6685f1a98880
Found-By: Coverity Scan #1405870
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Chromium flashrom fork has very poor dispatch logic whereas
upstream has proper inversion of control with a generic 'data'
void * member to stuff long-lived state in. Leverage the member
to store the USB descriptor state in during the life-time of the
spi master.
V.2: Remove unnecessary indirection as is the case in
commit a25c13cdb601f9d43b0f8edad96f9489efcb4b37.
BUG=b:140394053
BRANCH=none
TEST=builds && detects flashchip name.
Change-Id: Ida9dce97fef2c6dfd68a278c879917fdd3ff7fef
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40105
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
