Print an error message and return if the read from emu_persistent_image
fails.
Change-Id: Icd1a72f9171e547f2081ba4bc53834a17ef7fcab
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1403912
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67849
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Since fread() returns the number of bytes read, this currently will only
check for errors if it returns 0 (i.e. the file was empty). However, it
is possible for fread() to encounter an error after reading a few bytes,
which this doesn't catch. Fix this by using fgets() instead, which will
return NULL if EOF or an error is encountered, and is simpler anyway.
Change-Id: I4f37c70e97149b87c6344e63a57d11ddde7638c4
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1403824
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67848
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The N25Q is a stacked device, so it requires 0xC4 to perform a die
erase.
Signed-off-by: Jacob Creedon <jcreedon@google.com>
Change-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67847
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We never read the first 'ret'. Let's check the first 'ret'
and exit if it failed.
Also, print the version only when the command succeeded.
Backported to libusb-v0 version (checking for CMD_LENGTH
instead of 0 return value).
Found-by: scan-build 7.0.1-8
Change-Id: I4aac5e1f3bd0604b079e1fdd9b7f09f1f4fc2d7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34403
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
For the physmap*() functions, NULL is considered valid return value.
Fixes a segmentation fault when DMI tables can't be mapped.
Tested on intel/eblake board with broken coreboot.
Change-Id: Ic403c2940c2b91acbd113f0acfa3ce9ef6c6bb6c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
All these variables are only used in the files they are defined in, so
they can be made static.
(Backported as it untangles aliased global objects.)
Change-Id: I1e55138adef540e9d3a2237aa5b289cb338c0608
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62612
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Instead of hard coding the test procedure on qa.coreboot.org, allow
running a script in the repo instead. The server is already adapted
to do that, so once there's a test_build.sh file in the toplevel
directory, it's run in place of the default operation.
The content of this change mirrors the default operation exactly so
should serve as a good starting point.
The script is executed in an encapsulate[0] context with the workspace,
/tmp and $HOME/.ccache writable, everything else read-only and
network disabled.
It should return 0 on success, anything else on failure, as is normal
for UNIX processes.
[0] https://review.coreboot.org/cgit/encapsulate.git
(Backported minus the Meson support)
Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62617
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Nico Huber <nico.h@gmx.de>
Calm a compiler warning on big-endian builds about the unused static
flashrom_layout_parse_fmap(). The guard is ugly but gets the job done.
We should forbid endian-specific code in the future, I guess.
Change-Id: Id3f4a57e027f88cc469ed50312adddcc8af71a63
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33297
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Don't use a device that has the same vendor ID, but a different
than requested product ID.
Fixes broken dediprog detection with TOMU in use.
Change-Id: I08c1c363ce2d6603e46efecc61d3910e02314fca
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/32892
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is an interim solution. We'll have to enable 4BA step-by-step for
each dediprog protocol version.
Change-Id: I08efcbb09ab3499ef6902a698e9ce3d6232237c4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
The full verification step was not accounting for sparse layouts.
Instead of the old contents, combine_image_by_layout() implicitly
assumed the new contents for unspecified regions.
Change-Id: I44e0cea621f2a3d4dc70fa7e93c52ed95e54014a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The erase (-E) feature is somehow a brute force method, but still, if we
are given a region to erase, we should make sure to restore surrounding
data if the erase block expands beyond the region.
It shares a lot of code with the write path. Though, experiments with
common functions have shown that it would make the whole function even
harder to read. Maybe we could add some abstraction if we ever need
similar code on a third path.
Change-Id: I5fc35310f0b090f218cd1d660e27fb39dd05c3c5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
GCC is picky about the comment being where the break should go.
Change-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6
Signed-off-by: Richard Hughes <richard@hughsie.com>
Reviewed-on: https://review.coreboot.org/c/30406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Leaving the `linux_spi` driver's unknown default is almost never what we
want and resulted in many support requests since Raspbian switched to a
default that is too high for most applications.
Change-Id: I9361b7c1a1ab8900a619b06e1dae14cd87eb56c2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested on a Supermicro X10SLM+-F. The flash chip has been read, written,
and erased many times without issue. Most boards with this chipset will
have the ME region locked, hence the selection of DEP.
Change-Id: I25126b94e691289a7b29dd81d5c864854a4e0245
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This never was a use case until now but the `--fmap` code makes it
obvious: Unaligned reads that were smaller than the `chunksize` here,
were extended without considering the length of the buffer read into.
With that fixed we run into the next problem: dediprog_spi_bulk_read()
shouldn't report an error when an empty read is unaligned.
Change-Id: Ie12b62499ebfdb467d5126c00d327c76077ddead
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested reading, writing and erasing the internal flash chip using an HP
Pavilion dv6-2125ef laptop with an Intel PM55 chipset. However, since
all ME-enabled chipsets are marked as DEP instead of OK, this one shall
follow suit as well.
Change-Id: I667ea970be11a35b480e0e7c69a1fdf9afa08762
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As per user `The_Raven Raven` on the mailing list. Since the added
values had some inconsistencies, the chips are marked as untested.
Change-Id: I6c26aafdca232110986334e85297d73d513600dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested on an ASRock H81M-HDS. The flash chip has been read, written, and
erased many times without issue. Most boards with this chipset will have
the ME region locked, hence the selection of DEP.
Change-Id: I30aae956b2851c741e59403f5e49b80b5ba7c5e4
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Similar to W25Q256FV, but it supports the native 4BA page program
instruction (12h). Note that the variant with QE enabled by default
shares the device ID of the W25Q256FV.
Tested using a Raspberry Pi.
Change-Id: I76d7362777d364594d2a733d7e478741b0bef7c4
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/29305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Flashmap, or simply fmap, is a binary data format for describing
region offsets, sizes, and certain attributes and is widely used by
coreboot. This patch adds support for the fmap data format version 1.1
and adds --fmap and --fmap-file arguments.
Using --fmap will make flashrom to search the ROM content for fmap
data. Using --fmap-file will make flashrom search a supplied file
for fmap data.
An example of how to update the COREBOOT region of a ROM:
flashrom -p programmer --fmap -w coreboot.rom -i COREBOOT
flashrom -p programmer --fmap-file coreboot.rom -w coreboot.rom -i COREBOOT
The fmap functions are mostly copied from cbfstool.
Currently it is made mutually exclusive with other layout options until
we are more clever about this input.
Change-Id: I0e7fad38ed79a84d41358e1f175c36d255786c12
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested reading, writing and erasing the internal flash chip using a
Toshiba L755 laptop with an Intel HM65. However, since all ME-enabled
chipsets are marked as DEP instead of OK, this one shall follow suit as
well.
Change-Id: I3fd62c3b4ee17a403cc3937422f3d850fd2878a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Port the code from chromeos flashrom.
Tested using W25Q128JVSIM in SPI mode.
Change-Id: I38397a0c831407afa21cddca8485664576fce92c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The IS25WP064 was tested successfully by Simon Buhrow as reported on
2018-9-4. While we are at it, also add the 32Mbit version which shares
the datasheet (as does the already supported 128Mbit version).
Change-Id: Ie0887b4ae6e6465118a5dc2e20b784f783d161b8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
4BA mode is entered by setting bit 7 for the extended address register.
Change-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
The Spansion 25SFL256S supports 4BA through an extended address register,
a 4BA mode set by bit 7 of that register, or native 4BA instructions.
Enable the former only for now.
Unfortunately the S25SF256S uses another instruction to write the exten-
ded address register. So we add an override for the instruction byte.
Change-Id: I0a95a81dfe86434f049215ebd8477392391b9efc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Tested-by: Michael Fuckner <michael@fuckner.net>
Reviewed-on: https://review.coreboot.org/25132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
