1
0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 15:12:36 +02:00

189 Commits

Author SHA1 Message Date
Stefan Reinauer
7f27464c8a Adding support for flashing system with Nvidia MCP67
Corresponding to flashrom svn r298 and coreboot v2 svn r3414.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2008-07-05 09:48:30 +00:00
Stefan Reinauer
2cb94e183b First attempt to clean up SPI probing and create a common construct: the flash bus
At some point the flash bus will be part of struct flashchip.

Pardon me for pushing this in, but I think it is important to beware of further
decay and it will improve things for other developers in the short run.

Carl-Daniel, I will consider your suggestions in another patch. I want to keep
things from getting too much for now. The patch includes Rudolf's VIA SPI
changes though.

Corresponding to flashrom svn r285 and coreboot v2 svn r3401.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2008-06-30 23:45:22 +00:00
Rudolf Marek
3fdbccf697 This patch adds support for VIA SPI controller on VT8237S
It is similar with few documented exceptions to ICH7 SPI controller.

Corresponding to flashrom svn r282 and coreboot v2 svn r3398.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
2008-06-30 21:38:30 +00:00
Peter Stuge
7e2c079367 Fix ICH7 non-SPI that broke in r3393
r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back
to 0 when BOOT BIOS Straps indicate something else than SPI.

Also fixes a build error in ichspi.c with gcc 4.2.2.

Corresponding to flashrom svn r280 and coreboot v2 svn r3395.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2008-06-29 01:30:41 +00:00
Stefan Reinauer
a9424d597d Multiple unrelated changes
* ICH7 SPI support
* fix some variable names in ichspi.c (Offset -> offset)
* Dump ICH7 SPI bar with -V
* Improve error message in case IOPL goes wrong. (It might not even be an IOPL)

Corresponding to flashrom svn r278 and coreboot v2 svn r3393.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
2008-06-27 16:28:34 +00:00
Uwe Hermann
793bdcd71e A bunch of cosmetic improvements
- Fix typos and inconsistencies.
 - Drop duplicate line which tells us the chip name twice.
 - Also print the chip vendor, not only the name.

Corresponding to flashrom svn r249 and coreboot v2 svn r3348.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2008-05-22 22:47:04 +00:00
Andriy Gapon
65c1b86fe7 Changes to make flashrom compile (and work) on FreeBSD
This patch addresses different argument order of outX() calls,
FreeBSD-specific headers, difference in certain type names and system
interface names, and also FreeBSD-specific way of gaining IO port
access.

Corresponding to flashrom svn r245 and coreboot v2 svn r3344.

Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2008-05-22 13:22:45 +00:00
Carl-Daniel Hailfinger
1b18b3c076 ICH8 and ICH9 have an almost identical SPI interface, only the location of the SPIBAR differs
Add ICH8 support to the ICH9 code.

Corresponding to flashrom svn r241 and coreboot v2 svn r3327.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2008-05-16 14:39:39 +00:00
Dominik Geyer
b46acba6e0 Add support for SPI chips on ICH9
This is done by using the generic SPI interface.

Corresponding to flashrom svn r239 and coreboot v2 svn r3325.

Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2008-05-16 12:55:55 +00:00
Carl-Daniel Hailfinger
6dc1d3b8dc Add more infrastructure for flashrom ICH9 support
Corresponding to flashrom svn r234 and coreboot v2 svn r3314.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2008-05-14 14:51:22 +00:00
Claus Gindhart
a00e2a0edf Add the Intel 6300ESB as known chipset to the chipset struct enables
Corresponding to flashrom svn r233 and coreboot v2 svn r3310.

Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
2008-05-14 12:22:38 +00:00
Bari Ari
9477c4eca5 Enable ROM decode range to 1MB for vt8237r
Corresponding to flashrom svn r220 and coreboot v2 svn r3275.

Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2008-04-29 13:46:38 +00:00
Carl-Daniel Hailfinger
b36a071717 Add ICH9 detection
Straight from the datasheet, untested.

Corresponding to flashrom svn r215 and coreboot v2 svn r3167.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2008-03-18 00:54:10 +00:00
Carl-Daniel Hailfinger
67f9ea3b71 Prepare for ICH7/ICH8 SPI support by adding some debugging for all ICH* chipsets
Functionality (except printing) should be unchanged.

Corresponding to flashrom svn r207 and coreboot v2 svn r3144.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Ward says:
This code detects the ICH8 chipset on my laptop, and it appears to use
SPI.

Acked-by: Ward Vandewege <ward@gnu.org>
2008-03-14 17:20:59 +00:00
Uwe Hermann
eac1016437 Also print the chip vendor name in --list-supported output
Cosmetic changes in some files, partly bending the 80-characters-per-line
rule in this special case, as the 80-character-limited version looks
equally crappy even in an 80x25 console/xterm, so let's make it at least
look good in a high-resolution xterm.

Corresponding to flashrom svn r203 and coreboot v2 svn r3139.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2008-03-13 18:52:51 +00:00
Uwe Hermann
e5ac16445f Add --list-supported option which lists the supported ROM chips, chipsets, and mainboards
Corresponding to flashrom svn r199 and coreboot v2 svn r3133.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>
2008-03-12 11:54:51 +00:00
Mart Raudsepp
3697ac75d5 Further cleanups to enable_flash_cs5536
- Remove the "enable write to flash" message, as the caller appears to
   already report that.

 - Move the 'modprobe msr' suggestions to the first lseek64 error handling, as
   we get an error there already.

 - Rename a perror string from "read" to "read msr", as we use the latter
   already in this function for another read.

Corresponding to flashrom svn r195 and coreboot v2 svn r3101.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2008-02-11 14:32:45 +00:00
Mart Raudsepp
e1344da898 Improve error handling and make RCONF_DEFAULT_MSR address be a constant
Also, move a big code comment to the top of enable_flash_cs5536().

Corresponding to flashrom svn r193 and coreboot v2 svn r3098.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2008-02-08 10:10:57 +00:00
Mart Raudsepp
0514a5f07a Write enable flash chips attached to CS3 of CS5536 chipsets (AMD Geode)
This implements support for devices using AMD Geode companion chip
CS5536 that have the Boot ROM on NOR flash that is directly connected to
FLASH_CS3 (Boot Flash Chip Select). We need to write enable it in the
NORF_CTL MSR register for flashrom to be able to write to it, including
JEDEC probe commands.

This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on
the DBE61.

Corresponding to flashrom svn r192 and coreboot v2 svn r3097.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2008-02-08 09:59:58 +00:00
Marc Jones
3ac76af6f0 Correctly disable the ROM area Write Protect bit in the Geode LX
Corresponding to flashrom svn r188 and coreboot v2 svn r3078.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>

Tested on the pcengines alix1c and works fine.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
2008-01-26 07:35:47 +00:00
Uwe Hermann
372eeb5710 Various coding style fixes, constification, fixed typos
Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per
http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html

Corresponding to flashrom svn r162 and coreboot v2 svn r2997.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2007-12-04 21:49:06 +00:00
Lane Brooks
d54958a3c4 Flashrom support for AMD Geode CS5536
Attached is a patch that enables AMD Geode CS5536 chipset support.  I
have tested it successfully on a MSM800 board from digital logic.

Corresponding to flashrom svn r160 and coreboot v2 svn r2967.

Signed-off-by: Lane Brooks <lbrooks@mit.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
2007-11-13 16:45:22 +00:00
Uwe Hermann
97a647014d Add support for Intel 440MX and Fujitsu MBM29F400TC
Detection and reading works, writing is not tested.

Corresponding to flashrom svn r158 and coreboot v2 svn r2903.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
2007-10-30 00:56:50 +00:00
Uwe Hermann
a502dcea3d Some cosmetic cleanups in the flashrom code and output
Corresponding to flashrom svn r151 and coreboot v2 svn r2873.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2007-10-17 23:55:15 +00:00
Carl-Daniel Hailfinger
dca0ab1884 Fix wrong values/typos in chipset_enable.c
This has been confirmed by Ed Swierk in
http://www.mail-archive.com/linuxbios@linuxbios.org/msg09788.html .

Corresponding to flashrom svn r150 and coreboot v2 svn r2868.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2007-10-17 22:30:07 +00:00
Uwe Hermann
ac30934194 Revert my last cleanup patch
Corresponding to flashrom svn r143 and coreboot v2 svn r2847.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2007-10-10 17:42:20 +00:00
Uwe Hermann
17d00abf0a Cosmetic changes to make the flashrom output more consistent
Corresponding to flashrom svn r142 and coreboot v2 svn r2846.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2007-10-10 16:31:30 +00:00
Alex Beregszaszi
c9fb5d92e2 Change out/in combinations to pci_read/write_byte in sis630 chipset enable
Corresponding to flashrom svn r138 and coreboot v2 svn r2770.

Signed-off-by: Alex Beregszaszi <alex@rtfs.hu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2007-09-11 15:58:18 +00:00
Uwe Hermann
d110764ccd Change all flashrom license headers to use our standard format
No changes in content of the files.

Corresponding to flashrom svn r131 and coreboot v2 svn r2751.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2007-08-29 17:52:32 +00:00
Uwe Hermann
ffec5f3ab7 Cosmetic fixes
Corresponding to flashrom svn r130 and coreboot v2 svn r2748.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2007-08-23 16:08:21 +00:00
Uwe Hermann
0846f89b0a Drop a bunch of useless header files, merge them into flash.h
Corresponding to flashrom svn r128 and coreboot v2 svn r2746.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2007-08-23 13:34:59 +00:00
Uwe Hermann
f4a673b0cf Fix up and document the AMD CS5530/CS5530A support
The previous code was pretty unreadable, undocumented and did some totally
unrelated things (such as mucking with the game port or port 0x92).

This version is tested with a 256 KB chip and should work for the
CS5530 and CS5530A.

Corresponding to flashrom svn r120 and coreboot v2 svn r2715.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2007-06-06 21:35:45 +00:00
Uwe Hermann
e823ee0fc5 Document the newly supported IBM x3455 board and the now-supported Broadcom HT-1000 chipset
Corresponding to flashrom svn r119 and coreboot v2 svn r2713.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2007-06-05 15:02:18 +00:00
Stefan Reinauer
1c283f4241 Move GPIO settings to board specific code for IBM x3455
Corresponding to flashrom svn r118 and coreboot v2 svn r2712.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2007-06-05 12:51:52 +00:00
Stefan Reinauer
c868b9e68b Add support for BCM HT1000 chipset
Tested on IBM x3455.

Corresponding to flashrom svn r117 and coreboot v2 svn r2711.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2007-06-05 10:28:39 +00:00
Luc Verhaegen
6b14175ead Add support for ASUS P5A (Socket 7, ALi based)
* Add support for the ALi M1533 to chipset_enable.c
* Add some SMBus poking needed for the ASUS P5A, to board_enable.c

Since PCI subsystem IDs are worthless with this board, people will
have to name the board directly.

Corresponding to flashrom svn r109 and coreboot v2 svn r2677.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2007-05-20 16:16:13 +00:00
Uwe Hermann
a7e0548cea Fix coding style of flashrom by running indent on all files
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs *.[ch]

Some minor fixups were required, and maybe a few more cosmetic
changes are needed.

Corresponding to flashrom svn r108 and coreboot v2 svn r2643.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
2007-05-09 10:17:44 +00:00
Randall Philipson
c03106603a Add support for CX700 builtin southbridge
Corresponding to flashrom svn r101 and coreboot v2 svn r2599.

Signed-off-by: Randall Philipson <rtphilipson@cox.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2007-04-09 22:27:45 +00:00
Luc Verhaegen
8e3a600123 Split flash_enable.c into chipset_enable.c and board_enable.c
This splits up the ROM Write enable code into chipset specific and
board specific parts. This of course means that a lot of code is
plainly moved about.

* Allows for linuxbios name matching and pci-subsystem id matching.
  The latter uses a double set to properly distuinguish boards despite
  of some known vendors being lax about it.
* Fixes GPIO15 being raised on every VT8235 southbridge, regardless of what
  that line actually controls; rom on EPIA-M, backlight on mitac 8999 laptop.
* Adds flashrom support for Asus A7V400-MX (KM400 + VT8235)
* Island aruma was renamed agami aruma, the board specific code now got
  adjusted. A set of pci-ids was retrieved from source code.

Corresponding to flashrom svn r99 and coreboot v2 svn r2581.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
2007-04-04 22:45:58 +00:00