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If the flash chip is larger than 16MiB, the memory mapped read from top of 4G address will not work properly, resulting in accesses to addresses below 0xff000000. In such cases flashrom fails with "Bus error". Fallback to default_spi_read for flashes larger than 16 MiB. Using memory mapped access with ROM3 register could be implemented, however it introduces the complexity of ROM page remapping. I.e. the PSP may remap 16MiB pages of 32MiB or larger flashes by XORing the host memory mapped address bits [31:24]. It results in non-linear memory mapped flash space. Fixes the issue: https://ticket.coreboot.org/issues/370 TEST=Read complete flash content on Gigabyte MZ33-AR1 running coreboot. Change-Id: I218a4c2dbf7cd7e8fa25b3ecb5aeac03f54f9dc6 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/89446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>