mirror of
https://review.coreboot.org/flashrom.git
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823096e527
The Wildcat Point PCH can be paired with Broadwell or Haswell. This patch was essentially backported from ChromiumOS commit 9bd2af8. Corresponding to flashrom svn r1845. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
603 lines
14 KiB
C
603 lines
14 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de>
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* Copyright (c) 2011 Stefan Tauner
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#ifndef __ICH_DESCRIPTORS_H__
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#define __ICH_DESCRIPTORS_H__ 1
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#include <stdint.h>
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#include "programmer.h" /* for enum ich_chipset */
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/* FIXME: Replace with generic return codes */
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#define ICH_RET_OK 0
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#define ICH_RET_ERR -1
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#define ICH_RET_WARN -2
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#define ICH_RET_PARAM -3
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#define ICH_RET_OOB -4
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#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */
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/* 0-1: reserved */
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#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */
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#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF)
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#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */
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#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF)
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/* 15-31: reserved */
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#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */
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/* Field locations and semantics for LVSCC, UVSCC and related words in the flash
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* descriptor are equal therefore they all share the same macros below. */
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#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */
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#define VSCC_BES (0x3 << VSCC_BES_OFF)
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#define VSCC_WG_OFF 2 /* 2: Write Granularity */
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#define VSCC_WG (0x1 << VSCC_WG_OFF)
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#define VSCC_WSR_OFF 3 /* 3: Write Status Required */
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#define VSCC_WSR (0x1 << VSCC_WSR_OFF)
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#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */
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#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF)
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/* 5-7: reserved */
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#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */
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#define VSCC_EO (0xff << VSCC_EO_OFF)
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/* 16-22: reserved */
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#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */
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#define VSCC_VCL (0x1 << VSCC_VCL_OFF)
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/* 24-31: reserved */
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#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000)
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#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000)
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void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl);
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struct ich_desc_content {
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uint32_t FLVALSIG; /* 0x00 */
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union { /* 0x04 */
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uint32_t FLMAP0;
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struct {
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uint32_t FCBA :8, /* Flash Component Base Address */
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NC :2, /* Number Of Components */
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:6,
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FRBA :8, /* Flash Region Base Address */
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NR :3, /* Number Of Regions */
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:5;
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};
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};
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union { /* 0x08 */
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uint32_t FLMAP1;
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struct {
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uint32_t FMBA :8, /* Flash Master Base Address */
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NM :3, /* Number Of Masters */
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:5,
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FISBA :8, /* Flash ICH Strap Base Address */
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ISL :8; /* ICH Strap Length */
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};
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};
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union { /* 0x0c */
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uint32_t FLMAP2;
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struct {
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uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */
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MSL :8, /* MCH Strap Length */
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:16;
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};
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};
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};
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struct ich_desc_component {
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union { /* 0x00 */
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uint32_t FLCOMP; /* Flash Components Register */
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/* FLCOMP encoding on various generations:
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*
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* Chipset/Generation max_speed dual_output density
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* [MHz] bits max. bits
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* ICH8: 33 N/A 5 0:2, 3:5
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* ICH9: 33 N/A 5 0:2, 3:5
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* ICH10: 33 N/A 5 0:2, 3:5
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* Ibex Peak/5: 50 N/A 5 0:2, 3:5
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* Cougar Point/6: 50 30 5 0:2, 3:5
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* Patsburg: 50 30 5 0:2, 3:5
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* Panther Point/7 50 30 5 0:2, 3:5
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* Lynx Point/8: 50 30 7 0:3, 4:7
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* Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:?
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*/
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struct {
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uint32_t :17,
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freq_read :3,
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fastread :1,
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freq_fastread :3,
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freq_write :3,
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freq_read_id :3,
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:2;
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} common;
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struct {
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uint32_t comp1_density :3,
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comp2_density :3,
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:11,
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:13,
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:2;
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} old;
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struct {
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uint32_t comp1_density :4, /* new since Lynx Point/8 */
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comp2_density :4,
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:9,
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:13,
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dual_output :1, /* new since Cougar Point/6 */
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:1;
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} new;
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};
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union { /* 0x04 */
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uint32_t FLILL; /* Flash Invalid Instructions Register */
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struct {
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uint32_t invalid_instr0 :8,
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invalid_instr1 :8,
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invalid_instr2 :8,
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invalid_instr3 :8;
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};
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};
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union { /* 0x08 */
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uint32_t FLPB; /* Flash Partition Boundary Register */
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struct {
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uint32_t FPBA :13, /* Flash Partition Boundary Addr */
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:19;
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};
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};
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};
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struct ich_desc_region {
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union {
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uint32_t FLREGs[5];
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struct {
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struct { /* FLREG0 Flash Descriptor */
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uint32_t reg0_base :13,
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:3,
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reg0_limit :13,
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:3;
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};
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struct { /* FLREG1 BIOS */
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uint32_t reg1_base :13,
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:3,
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reg1_limit :13,
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:3;
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};
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struct { /* FLREG2 ME */
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uint32_t reg2_base :13,
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:3,
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reg2_limit :13,
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:3;
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};
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struct { /* FLREG3 GbE */
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uint32_t reg3_base :13,
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:3,
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reg3_limit :13,
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:3;
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};
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struct { /* FLREG4 Platform */
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uint32_t reg4_base :13,
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:3,
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reg4_limit :13,
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:3;
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};
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};
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};
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};
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struct ich_desc_master {
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union {
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uint32_t FLMSTR1;
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struct {
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uint32_t BIOS_req_ID :16,
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BIOS_descr_r :1,
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BIOS_BIOS_r :1,
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BIOS_ME_r :1,
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BIOS_GbE_r :1,
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BIOS_plat_r :1,
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:3,
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BIOS_descr_w :1,
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BIOS_BIOS_w :1,
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BIOS_ME_w :1,
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BIOS_GbE_w :1,
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BIOS_plat_w :1,
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:3;
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};
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};
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union {
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uint32_t FLMSTR2;
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struct {
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uint32_t ME_req_ID :16,
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ME_descr_r :1,
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ME_BIOS_r :1,
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ME_ME_r :1,
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ME_GbE_r :1,
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ME_plat_r :1,
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:3,
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ME_descr_w :1,
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ME_BIOS_w :1,
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ME_ME_w :1,
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ME_GbE_w :1,
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ME_plat_w :1,
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:3;
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};
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};
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union {
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uint32_t FLMSTR3;
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struct {
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uint32_t GbE_req_ID :16,
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GbE_descr_r :1,
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GbE_BIOS_r :1,
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GbE_ME_r :1,
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GbE_GbE_r :1,
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GbE_plat_r :1,
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:3,
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GbE_descr_w :1,
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GbE_BIOS_w :1,
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GbE_ME_w :1,
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GbE_GbE_w :1,
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GbE_plat_w :1,
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:3;
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};
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};
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};
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#ifdef ICH_DESCRIPTORS_FROM_DUMP
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struct ich_desc_north_strap {
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union {
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uint32_t STRPs[1]; /* current maximum: ich8 */
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struct { /* ich8 */
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struct { /* STRP2 (in the datasheet) */
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uint32_t MDB :1,
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:31;
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};
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} ich8;
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};
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};
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struct ich_desc_south_strap {
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union {
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uint32_t STRPs[18]; /* current maximum: cougar point */
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struct { /* ich8 */
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struct { /* STRP1 */
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uint32_t ME_DISABLE :1,
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:6,
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TCOMODE :1,
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ASD :7,
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BMCMODE :1,
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:3,
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GLAN_PCIE_SEL :1,
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GPIO12_SEL :2,
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SPICS1_LANPHYPC_SEL :1,
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MESM2SEL :1,
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:1,
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ASD2 :7;
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};
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} ich8;
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struct { /* ibex peak */
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struct { /* STRP0 */
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uint32_t :1,
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cs_ss2 :1,
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:5,
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SMB_EN :1,
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SML0_EN :1,
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SML1_EN :1,
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SML1FRQ :2,
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SMB0FRQ :2,
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SML0FRQ :2,
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:4,
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LANPHYPC_GP12_SEL :1,
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cs_ss1 :1,
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:2,
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DMI_REQID_DIS :1,
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:4,
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BBBS :2,
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:1;
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};
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struct { /* STRP1 */
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uint32_t cs_ss3 :4,
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:28;
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};
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struct { /* STRP2 */
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uint32_t :8,
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MESMASDEN :1,
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MESMASDA :7,
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:8,
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MESMI2CEN :1,
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MESMI2CA :7;
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};
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struct { /* STRP3 */
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uint32_t :32;
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};
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struct { /* STRP4 */
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uint32_t PHYCON :2,
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:6,
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GBEMAC_SMBUS_ADDR_EN :1,
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GBEMAC_SMBUS_ADDR :7,
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:1,
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GBEPHY_SMBUS_ADDR :7,
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:8;
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};
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struct { /* STRP5 */
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uint32_t :32;
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};
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struct { /* STRP6 */
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uint32_t :32;
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};
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struct { /* STRP7 */
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uint32_t MESMA2UDID_VENDOR :16,
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MESMA2UDID_DEVICE :16;
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};
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struct { /* STRP8 */
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uint32_t :32;
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};
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struct { /* STRP9 */
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uint32_t PCIEPCS1 :2,
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PCIEPCS2 :2,
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PCIELR1 :1,
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PCIELR2 :1,
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DMILR :1,
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:1,
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PHY_PCIEPORTSEL :3,
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PHY_PCIE_EN :1,
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:20;
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};
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struct { /* STRP10 */
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uint32_t :1,
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ME_BOOT_FLASH :1,
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cs_ss5 :1,
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VE_EN :1,
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:4,
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MMDDE :1,
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MMADDR :7,
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cs_ss7 :1,
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:1,
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ICC_SEL :3,
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MER_CL1 :1,
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:10;
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};
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struct { /* STRP11 */
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uint32_t SML1GPAEN :1,
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SML1GPA :7,
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:16,
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SML1I2CAEN :1,
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SML1I2CA :7;
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};
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struct { /* STRP12 */
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uint32_t :32;
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};
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struct { /* STRP13 */
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uint32_t :32;
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};
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struct { /* STRP14 */
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uint32_t :8,
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VE_EN2 :1,
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:5,
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VE_BOOT_FLASH :1,
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:1,
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BW_SSD :1,
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NVMHCI_EN :1,
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:14;
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};
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struct { /* STRP15 */
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uint32_t :3,
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cs_ss6 :2,
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:1,
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IWL_EN :1,
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:1,
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t209min :2,
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:22;
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};
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} ibex;
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struct { /* cougar point */
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struct { /* STRP0 */
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uint32_t :1,
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cs_ss1 :1,
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:5,
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SMB_EN :1,
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SML0_EN :1,
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SML1_EN :1,
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SML1FRQ :2,
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SMB0FRQ :2,
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SML0FRQ :2,
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:4,
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LANPHYPC_GP12_SEL :1,
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LINKSEC_DIS :1,
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:2,
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DMI_REQID_DIS :1,
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:4,
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BBBS :2,
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:1;
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};
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struct { /* STRP1 */
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uint32_t cs_ss3 :4,
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:4,
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cs_ss2 :1,
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:28;
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};
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struct { /* STRP2 */
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uint32_t :8,
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MESMASDEN :1,
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MESMASDA :7,
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MESMMCTPAEN :1,
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MESMMCTPA :7,
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MESMI2CEN :1,
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MESMI2CA :7;
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};
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struct { /* STRP3 */
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uint32_t :32;
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};
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struct { /* STRP4 */
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uint32_t PHYCON :2,
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:6,
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GBEMAC_SMBUS_ADDR_EN :1,
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GBEMAC_SMBUS_ADDR :7,
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:1,
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GBEPHY_SMBUS_ADDR :7,
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:8;
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};
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struct { /* STRP5 */
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uint32_t :32;
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};
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struct { /* STRP6 */
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uint32_t :32;
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};
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struct { /* STRP7 */
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uint32_t MESMA2UDID_VENDOR :16,
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MESMA2UDID_DEVICE :16;
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};
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struct { /* STRP8 */
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uint32_t :32;
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};
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struct { /* STRP9 */
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uint32_t PCIEPCS1 :2,
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PCIEPCS2 :2,
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PCIELR1 :1,
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PCIELR2 :1,
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DMILR :1,
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cs_ss4 :1,
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PHY_PCIEPORTSEL :3,
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PHY_PCIE_EN :1,
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:2,
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SUB_DECODE_EN :1,
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:7,
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PCHHOT_SML1ALERT_SEL :1,
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:9;
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};
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struct { /* STRP10 */
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uint32_t :1,
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ME_BOOT_FLASH :1,
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:6,
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MDSMBE_EN :1,
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MDSMBE_ADD :7,
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:2,
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ICC_SEL :3,
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MER_CL1 :1,
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ICC_PRO_SEL :1,
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Deep_SX_EN :1,
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ME_DBG_LAN :1,
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:7;
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};
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struct { /* STRP11 */
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uint32_t SML1GPAEN :1,
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SML1GPA :7,
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:16,
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SML1I2CAEN :1,
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SML1I2CA :7;
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};
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struct { /* STRP12 */
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uint32_t :32;
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};
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struct { /* STRP13 */
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uint32_t :32;
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};
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struct { /* STRP14 */
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uint32_t :32;
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};
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struct { /* STRP15 */
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uint32_t cs_ss6 :6,
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IWL_EN :1,
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cs_ss5 :2,
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:4,
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SMLINK1_THERM_SEL :1,
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SLP_LAN_GP29_SEL :1,
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:16;
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};
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struct { /* STRP16 */
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uint32_t :32;
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};
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struct { /* STRP17 */
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uint32_t ICML :1,
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cs_ss7 :1,
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:30;
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};
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} cougar;
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};
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};
|
|
|
|
struct ich_desc_upper_map {
|
|
union {
|
|
uint32_t FLUMAP1; /* Flash Upper Map 1 */
|
|
struct {
|
|
uint32_t VTBA :8, /* ME VSCC Table Base Address */
|
|
VTL :8, /* ME VSCC Table Length */
|
|
:16;
|
|
};
|
|
};
|
|
struct {
|
|
union { /* JEDEC-ID Register */
|
|
uint32_t JID;
|
|
struct {
|
|
uint32_t vid :8, /* Vendor ID */
|
|
cid0 :8, /* Component ID 0 */
|
|
cid1 :8, /* Component ID 1 */
|
|
:8;
|
|
};
|
|
};
|
|
union { /* Vendor Specific Component Capabilities */
|
|
uint32_t VSCC;
|
|
struct {
|
|
uint32_t ubes :2, /* Upper Block/Sector Erase Size */
|
|
uwg :1, /* Upper Write Granularity */
|
|
uwsr :1, /* Upper Write Status Required */
|
|
uwews :1, /* Upper Write Enable on Write Status */
|
|
:3,
|
|
ueo :8, /* Upper Erase Opcode */
|
|
lbes :2, /* Lower Block/Sector Erase Size */
|
|
lwg :1, /* Lower Write Granularity */
|
|
lwsr :1, /* Lower Write Status Required */
|
|
lwews :1, /* Lower Write Enable on Write Status */
|
|
:3,
|
|
leo :16; /* Lower Erase Opcode */
|
|
};
|
|
};
|
|
} vscc_table[128];
|
|
};
|
|
#endif /* ICH_DESCRIPTORS_FROM_DUMP */
|
|
|
|
struct ich_descriptors {
|
|
struct ich_desc_content content;
|
|
struct ich_desc_component component;
|
|
struct ich_desc_region region;
|
|
struct ich_desc_master master;
|
|
#ifdef ICH_DESCRIPTORS_FROM_DUMP
|
|
struct ich_desc_north_strap north;
|
|
struct ich_desc_south_strap south;
|
|
struct ich_desc_upper_map upper;
|
|
#endif /* ICH_DESCRIPTORS_FROM_DUMP */
|
|
};
|
|
|
|
void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc);
|
|
|
|
void prettyprint_ich_descriptor_content(const struct ich_desc_content *content);
|
|
void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc);
|
|
void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc);
|
|
void prettyprint_ich_descriptor_master(const struct ich_desc_master *master);
|
|
|
|
#ifdef ICH_DESCRIPTORS_FROM_DUMP
|
|
|
|
void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap);
|
|
void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc);
|
|
int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struct ich_descriptors *desc);
|
|
|
|
#else /* ICH_DESCRIPTORS_FROM_DUMP */
|
|
|
|
int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc);
|
|
int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx);
|
|
|
|
#endif /* ICH_DESCRIPTORS_FROM_DUMP */
|
|
#endif /* __ICH_DESCRIPTORS_H__ */
|
|
#endif /* defined(__i386__) || defined(__x86_64__) */
|