mirror of
https://review.coreboot.org/flashrom.git
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89edf36c17
This is mostly a leftover of Niklas' "remove exit call from pcidev_init" patch. While not explicitly necessary detecting errors early is usually a good idea. Corresponding to flashrom svn r1718. Signed-off-by: Niklas Söderlund <niso@kth.se> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
146 lines
3.9 KiB
C
146 lines
3.9 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2010 Mark Marshall
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdlib.h>
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#include <strings.h>
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#include <string.h>
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#include "flash.h"
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#include "programmer.h"
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#include "hwaccess.h"
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#define PCI_VENDOR_ID_OGP 0x1227
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/* These are the register addresses for the OGD1 / OGA1. If they are
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* different for later versions of the hardware then we will need
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* logic to select between the different hardware versions. */
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#define OGA1_XP10_BPROM_SI 0x0040 /* W */
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#define OGA1_XP10_BPROM_SO 0x0040 /* R */
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#define OGA1_XP10_BPROM_CE_BAR 0x0044 /* W */
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#define OGA1_XP10_BPROM_SCK 0x0048 /* W */
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#define OGA1_XP10_BPROM_REG_SEL 0x004C /* W */
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#define OGA1_XP10_CPROM_SI 0x0050 /* W */
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#define OGA1_XP10_CPROM_SO 0x0050 /* R */
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#define OGA1_XP10_CPROM_CE_BAR 0x0054 /* W */
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#define OGA1_XP10_CPROM_SCK 0x0058 /* W */
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#define OGA1_XP10_CPROM_REG_SEL 0x005C /* W */
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static uint8_t *ogp_spibar;
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static uint32_t ogp_reg_sel;
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static uint32_t ogp_reg_siso;
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static uint32_t ogp_reg__ce;
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static uint32_t ogp_reg_sck;
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const struct dev_entry ogp_spi[] = {
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{PCI_VENDOR_ID_OGP, 0x0000, OK, "Open Graphics Project", "Development Board OGD1"},
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{0},
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};
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static void ogp_request_spibus(void)
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{
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pci_mmio_writel(1, ogp_spibar + ogp_reg_sel);
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}
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static void ogp_release_spibus(void)
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{
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pci_mmio_writel(0, ogp_spibar + ogp_reg_sel);
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}
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static void ogp_bitbang_set_cs(int val)
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{
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pci_mmio_writel(val, ogp_spibar + ogp_reg__ce);
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}
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static void ogp_bitbang_set_sck(int val)
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{
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pci_mmio_writel(val, ogp_spibar + ogp_reg_sck);
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}
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static void ogp_bitbang_set_mosi(int val)
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{
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pci_mmio_writel(val, ogp_spibar + ogp_reg_siso);
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}
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static int ogp_bitbang_get_miso(void)
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{
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uint32_t tmp;
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tmp = pci_mmio_readl(ogp_spibar + ogp_reg_siso);
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return tmp & 0x1;
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}
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static const struct bitbang_spi_master bitbang_spi_master_ogp = {
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.type = BITBANG_SPI_MASTER_OGP,
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.set_cs = ogp_bitbang_set_cs,
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.set_sck = ogp_bitbang_set_sck,
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.set_mosi = ogp_bitbang_set_mosi,
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.get_miso = ogp_bitbang_get_miso,
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.request_bus = ogp_request_spibus,
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.release_bus = ogp_release_spibus,
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.half_period = 0,
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};
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int ogp_spi_init(void)
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{
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struct pci_dev *dev = NULL;
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char *type;
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type = extract_programmer_param("rom");
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if (!type) {
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msg_perr("Please use flashrom -p ogp_spi:rom=... to specify "
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"which flashchip you want to access.\n");
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return 1;
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} else if (!strcasecmp(type, "bprom") || !strcasecmp(type, "bios")) {
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ogp_reg_sel = OGA1_XP10_BPROM_REG_SEL;
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ogp_reg_siso = OGA1_XP10_BPROM_SI;
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ogp_reg__ce = OGA1_XP10_BPROM_CE_BAR;
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ogp_reg_sck = OGA1_XP10_BPROM_SCK;
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} else if (!strcasecmp(type, "cprom") || !strcasecmp(type, "s3")) {
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ogp_reg_sel = OGA1_XP10_CPROM_REG_SEL;
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ogp_reg_siso = OGA1_XP10_CPROM_SI;
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ogp_reg__ce = OGA1_XP10_CPROM_CE_BAR;
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ogp_reg_sck = OGA1_XP10_CPROM_SCK;
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} else {
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msg_perr("Invalid or missing rom= parameter.\n");
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return 1;
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}
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if (rget_io_perms())
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return 1;
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dev = pcidev_init(ogp_spi, PCI_BASE_ADDRESS_0);
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if (!dev)
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return 1;
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io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
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if (!io_base_addr)
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return 1;
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ogp_spibar = rphysmap("OGP registers", io_base_addr, 4096);
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if (ogp_spibar == ERROR_PTR)
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return 1;
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if (bitbang_spi_init(&bitbang_spi_master_ogp))
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return 1;
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return 0;
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}
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