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https://review.coreboot.org/flashrom.git
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89edf36c17
This is mostly a leftover of Niklas' "remove exit call from pcidev_init" patch. While not explicitly necessary detecting errors early is usually a good idea. Corresponding to flashrom svn r1718. Signed-off-by: Niklas Söderlund <niso@kth.se> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
142 lines
4.1 KiB
C
142 lines
4.1 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Datasheets can be found on http://www.siliconimage.com. Great thanks! */
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#include "programmer.h"
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#include "hwaccess.h"
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#define PCI_VENDOR_ID_SII 0x1095
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#define SATASII_MEMMAP_SIZE 0x100
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static uint8_t *sii_bar;
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static uint16_t id;
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const struct dev_entry satas_sii[] = {
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{0x1095, 0x0680, OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"},
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{0x1095, 0x3112, OK, "Silicon Image", "SiI 3112 [SATALink/SATARaid] SATA Ctrl"},
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{0x1095, 0x3114, OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"},
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{0x1095, 0x3124, OK, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"},
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{0x1095, 0x3132, OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"},
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{0x1095, 0x3512, OK, "Silicon Image", "SiI 3512 [SATALink/SATARaid] SATA Ctrl"},
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{0},
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};
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static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
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static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr);
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static const struct par_programmer par_programmer_satasii = {
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.chip_readb = satasii_chip_readb,
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.chip_readw = fallback_chip_readw,
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.chip_readl = fallback_chip_readl,
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.chip_readn = fallback_chip_readn,
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.chip_writeb = satasii_chip_writeb,
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.chip_writew = fallback_chip_writew,
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.chip_writel = fallback_chip_writel,
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.chip_writen = fallback_chip_writen,
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};
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static uint32_t satasii_wait_done(void)
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{
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uint32_t ctrl_reg;
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int i = 0;
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while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) {
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if (++i > 10000) {
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msg_perr("%s: control register stuck at %08x, ignoring.\n",
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__func__, pci_mmio_readl(sii_bar));
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break;
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}
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}
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return ctrl_reg;
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}
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int satasii_init(void)
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{
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struct pci_dev *dev = NULL;
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uint32_t addr;
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uint16_t reg_offset;
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if (rget_io_perms())
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return 1;
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dev = pcidev_init(satas_sii, PCI_BASE_ADDRESS_0);
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if (!dev)
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return 1;
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id = dev->device_id;
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if ((id == 0x3132) || (id == 0x3124)) {
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addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
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if (!addr)
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return 1;
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reg_offset = 0x70;
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} else {
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addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5);
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if (!addr)
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return 1;
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reg_offset = 0x50;
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}
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sii_bar = rphysmap("SATA SiI registers", addr, SATASII_MEMMAP_SIZE);
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if (sii_bar == ERROR_PTR)
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return 1;
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sii_bar += reg_offset;
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/* Check if ROM cycle are OK. */
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if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26))))
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msg_pwarn("Warning: Flash seems unconnected.\n");
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register_par_programmer(&par_programmer_satasii, BUS_PARALLEL);
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return 0;
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}
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static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
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{
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uint32_t data_reg;
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uint32_t ctrl_reg = satasii_wait_done();
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/* Mask out unused/reserved bits, set writes and start transaction. */
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ctrl_reg &= 0xfcf80000;
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ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);
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data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val;
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pci_mmio_writel(data_reg, (sii_bar + 4));
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pci_mmio_writel(ctrl_reg, sii_bar);
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satasii_wait_done();
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}
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static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr)
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{
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uint32_t ctrl_reg = satasii_wait_done();
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/* Mask out unused/reserved bits, set reads and start transaction. */
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ctrl_reg &= 0xfcf80000;
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ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);
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pci_mmio_writel(ctrl_reg, sii_bar);
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satasii_wait_done();
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return (pci_mmio_readl(sii_bar + 4)) & 0xff;
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}
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