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829c0e4e6a
Change-Id: Iaa222f9f265e019798aada4d556c484cb3b46b5d Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/89522 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jean THOMAS <virgule@jeanthomas.me> Reviewed-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Antonio Vázquez Blanco <antoniovazquezblanco@gmail.com>
123 lines
3.4 KiB
C
123 lines
3.4 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* SPDX-License-Identifier: GPL-2.0-only
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* SPDX-FileCopyrightText: 2011 Carl-Daniel Hailfinger
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*/
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/* Datasheet: http://download.intel.com/design/network/datashts/82559_Fast_Ethernet_Multifunction_PCI_Cardbus_Controller_Datasheet.pdf */
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#include <stdlib.h>
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#include "flash.h"
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#include "programmer.h"
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#include "hwaccess_physmap.h"
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#include "pcidev.h"
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struct nicintel_data {
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uint8_t *nicintel_bar;
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uint8_t *nicintel_control_bar;
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};
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static const struct dev_entry nics_intel[] = {
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{PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"},
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{PCI_VENDOR_ID_INTEL, 0x1229, OK, "Intel", "82557/8/9/0/1 Ethernet Pro 100"},
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{0},
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};
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/* Arbitrary limit, taken from the datasheet I just had lying around.
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* 128 kByte on the 82559 device. Or not. Depends on whom you ask.
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*/
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#define NICINTEL_MEMMAP_SIZE (128 * 1024)
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#define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1)
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#define NICINTEL_CONTROL_MEMMAP_SIZE 0x10
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#define CSR_FCR 0x0c
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static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
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chipaddr addr)
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{
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const struct nicintel_data *data = flash->mst->par.data;
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pci_mmio_writeb(val, data->nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
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}
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static uint8_t nicintel_chip_readb(const struct flashctx *flash,
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const chipaddr addr)
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{
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const struct nicintel_data *data = flash->mst->par.data;
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return pci_mmio_readb(data->nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
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}
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static int nicintel_shutdown(void *par_data)
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{
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free(par_data);
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return 0;
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}
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static const struct par_master par_master_nicintel = {
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.chip_readb = nicintel_chip_readb,
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.chip_writeb = nicintel_chip_writeb,
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.shutdown = nicintel_shutdown,
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};
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static int nicintel_init(const struct programmer_cfg *cfg)
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{
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struct pci_dev *dev = NULL;
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uintptr_t addr;
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uint8_t *bar;
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uint8_t *control_bar;
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/* FIXME: BAR2 is not available if the device uses the CardBus function. */
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dev = pcidev_init(cfg, nics_intel, PCI_BASE_ADDRESS_2);
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if (!dev)
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return 1;
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addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
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if (!addr)
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return 1;
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bar = rphysmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);
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if (bar == ERROR_PTR)
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return 1;
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addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
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if (!addr)
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return 1;
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control_bar = rphysmap("Intel NIC control/status reg", addr, NICINTEL_CONTROL_MEMMAP_SIZE);
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if (control_bar == ERROR_PTR)
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return 1;
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/* FIXME: This register is pretty undocumented in all publicly available
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* documentation from Intel. Let me quote the complete info we have:
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* "Flash Control Register: The Flash Control register allows the CPU to
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* enable writes to an external Flash. The Flash Control Register is a
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* 32-bit field that allows access to an external Flash device."
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* Ah yes, we also know where it is, but we have absolutely _no_ idea
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* what we should do with it. Write 0x0001 because we have nothing
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* better to do with our time.
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*/
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pci_rmmio_writew(0x0001, control_bar + CSR_FCR);
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struct nicintel_data *data = calloc(1, sizeof(*data));
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if (!data) {
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msg_perr("Unable to allocate space for PAR master data\n");
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return 1;
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}
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data->nicintel_bar = bar;
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data->nicintel_control_bar = control_bar;
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max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
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return register_par_master(&par_master_nicintel, BUS_PARALLEL, data);
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}
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const struct programmer_entry programmer_nicintel = {
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.name = "nicintel",
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.type = PCI,
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.devs.dev = nics_intel,
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.init = nicintel_init,
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};
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