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Q127C and Q128C are not the same. Q127C doesn't support QPI but Q128C does. So we need to split the existing GD25Q127C/GD25Q128C into two separated entries. We also introduce the new flashchip Q128E and merge it into Q127C. Datasheets: Q128E: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00480-GD25Q128E-Rev1.2.pdf Q127C: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00220-GD25Q127C-Rev2.3.pdf Q128C: https://www.endrich.com/sixcms/media.php/2/GD25Q128C-Rev2.pdf Q128E and Q127C/Q128C have compatible main functions, their differences are: * Q128E uses 55 nm process, while Q127C/Q128C use 65nm * Q128E/Q127C does not support QPI * Q128E/Q127C have OTP: 3072B, while Q128C are 1536B * Q128E's fast read clock frequency is 133MHz, while Q127C/Q128C are 104MHZ So we decided to merge Q128E into Q127C. We also tested that Q128E could pass flashrom_tester while probing it as 127C/128C, so the main functionalities are compatible. Change the chip name from GD25Q127C/GD25Q128C to two entries GD25Q127C/GD25Q128E and GD25Q128C to make it more accurate. Chip revision history: - The 'GD25Q127C/GD25Q128C' definition was added in `commit e0c7abf219b81ad049d09a4671ebc9196153d308` as 'GD25Q128C' and later renamed to 'GD25Q127C/GD25Q128C' BUG=b:304863141, b:293545382 BRANCH=none TEST=flashrom_tester with flashrom binary could pass with Q128E, which contains probe, read, write, erase, and write protect Signed-off-by: Hsuan Ting Chen <roccochen@google.com> Change-Id: I3300671b1cf74b3ea0469b9c5a833489ab4914f5 Reviewed-on: https://review.coreboot.org/c/flashrom/+/78348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>