mirror of
https://review.coreboot.org/flashrom.git
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Some SPI opcodes need to be sent in direct succession after each other without any chip deselect happening in between. A prominent example is WREN (Write Enable) directly before PP (Page Program). Intel calls the first opcode in such a row "preopcode". Right now, we ignore the direct succession requirement completely and it works pretty well because most onboard SPI masters have a timing or heuristics which make the problem disappear. The FT2232 SPI flasher is different. Since it is an external flasher, timing is very different to what we can expect from onboard flashers and this leads to failure at slow speeds. This patch allows any function to submit multiple SPI commands in a stream to any flasher. Support in the individual flashers isn't implemented yet, so there is one generic function which passes the each command in the stream one-by-one to the command functions of the selected SPI flash driver. Tested-by: Jakob Bornecrantz <wallbraker@gmail.com> Corresponding to flashrom svn r645. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Jakob Bornecrantz <wallbraker@gmail.com>
164 lines
4.3 KiB
C
164 lines
4.3 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2009 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <string.h>
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#include <stdlib.h>
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#include <ctype.h>
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#include <fcntl.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <errno.h>
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#include "flash.h"
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char *dummytype = NULL;
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int dummy_init(void)
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{
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int i;
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printf_debug("%s\n", __func__);
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/* "all" is equivalent to specifying no type. */
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if (dummytype && (!strcmp(dummytype, "all"))) {
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free(dummytype);
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dummytype = NULL;
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}
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if (!dummytype)
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dummytype = strdup("parallel,lpc,fwh,spi");
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/* Convert the parameters to lowercase. */
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for (i = 0; dummytype[i] != '\0'; i++)
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dummytype[i] = (char)tolower(dummytype[i]);
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buses_supported = CHIP_BUSTYPE_NONE;
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if (strstr(dummytype, "parallel")) {
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buses_supported |= CHIP_BUSTYPE_PARALLEL;
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printf_debug("Enabling support for %s flash.\n", "parallel");
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}
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if (strstr(dummytype, "lpc")) {
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buses_supported |= CHIP_BUSTYPE_LPC;
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printf_debug("Enabling support for %s flash.\n", "LPC");
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}
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if (strstr(dummytype, "fwh")) {
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buses_supported |= CHIP_BUSTYPE_FWH;
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printf_debug("Enabling support for %s flash.\n", "FWH");
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}
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if (strstr(dummytype, "spi")) {
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buses_supported |= CHIP_BUSTYPE_SPI;
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spi_controller = SPI_CONTROLLER_DUMMY;
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printf_debug("Enabling support for %s flash.\n", "SPI");
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}
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if (buses_supported == CHIP_BUSTYPE_NONE)
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printf_debug("Support for all flash bus types disabled.\n");
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free(dummytype);
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return 0;
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}
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int dummy_shutdown(void)
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{
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printf_debug("%s\n", __func__);
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return 0;
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}
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void *dummy_map(const char *descr, unsigned long phys_addr, size_t len)
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{
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printf_debug("%s: Mapping %s, 0x%lx bytes at 0x%08lx\n",
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__func__, descr, (unsigned long)len, phys_addr);
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return (void *)phys_addr;
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}
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void dummy_unmap(void *virt_addr, size_t len)
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{
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printf_debug("%s: Unmapping 0x%lx bytes at %p\n",
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__func__, (unsigned long)len, virt_addr);
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}
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void dummy_chip_writeb(uint8_t val, chipaddr addr)
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{
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printf_debug("%s: addr=0x%lx, val=0x%02x\n", __func__, addr, val);
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}
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void dummy_chip_writew(uint16_t val, chipaddr addr)
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{
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printf_debug("%s: addr=0x%lx, val=0x%04x\n", __func__, addr, val);
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}
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void dummy_chip_writel(uint32_t val, chipaddr addr)
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{
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printf_debug("%s: addr=0x%lx, val=0x%08x\n", __func__, addr, val);
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}
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void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len)
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{
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size_t i;
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printf_debug("%s: addr=0x%lx, len=0x%08lx, writing data (hex):",
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__func__, addr, (unsigned long)len);
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for (i = 0; i < len; i++) {
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if ((i % 16) == 0)
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printf_debug("\n");
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printf_debug("%02x ", buf[i])
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}
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}
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uint8_t dummy_chip_readb(const chipaddr addr)
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{
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printf_debug("%s: addr=0x%lx, returning 0xff\n", __func__, addr);
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return 0xff;
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}
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uint16_t dummy_chip_readw(const chipaddr addr)
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{
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printf_debug("%s: addr=0x%lx, returning 0xffff\n", __func__, addr);
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return 0xffff;
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}
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uint32_t dummy_chip_readl(const chipaddr addr)
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{
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printf_debug("%s: addr=0x%lx, returning 0xffffffff\n", __func__, addr);
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return 0xffffffff;
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}
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void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len)
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{
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printf_debug("%s: addr=0x%lx, len=0x%lx, returning array of 0xff\n",
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__func__, addr, (unsigned long)len);
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memset(buf, 0xff, len);
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return;
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}
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int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr)
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{
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int i;
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printf_debug("%s:", __func__);
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printf_debug(" writing %u bytes:", writecnt);
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for (i = 0; i < writecnt; i++)
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printf_debug(" 0x%02x", writearr[i]);
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printf_debug(" reading %u bytes:", readcnt);
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for (i = 0; i < readcnt; i++) {
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printf_debug(" 0xff");
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readarr[i] = 0xff;
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}
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printf_debug("\n");
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return 0;
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}
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