mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-30 00:13:43 +02:00
d0478299b1
Some SPI opcodes need to be sent in direct succession after each other without any chip deselect happening in between. A prominent example is WREN (Write Enable) directly before PP (Page Program). Intel calls the first opcode in such a row "preopcode". Right now, we ignore the direct succession requirement completely and it works pretty well because most onboard SPI masters have a timing or heuristics which make the problem disappear. The FT2232 SPI flasher is different. Since it is an external flasher, timing is very different to what we can expect from onboard flashers and this leads to failure at slow speeds. This patch allows any function to submit multiple SPI commands in a stream to any flasher. Support in the individual flashers isn't implemented yet, so there is one generic function which passes the each command in the stream one-by-one to the command functions of the selected SPI flash driver. Tested-by: Jakob Bornecrantz <wallbraker@gmail.com> Corresponding to flashrom svn r645. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Jakob Bornecrantz <wallbraker@gmail.com>
-------------------------------------------------------------------------------
flashrom README
-------------------------------------------------------------------------------
flashrom is a utility for reading, writing, verifying and erasing flash ROM
chips. It's often used to flash BIOS/EFI/coreboot/firmware images in-system
using a supported mainboard, but it also supports flashing of network
cards (NICs), SATA controller cards, and other external devices which can
program flash chips.
It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and
TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash,
or SPI.
(see http://coreboot.org for details on coreboot)
Packaging
---------
To package flashrom and remove dependencies on subversion, either use
make export
or
make tarball
make export will export all flashrom files from the subversion repository at
revision BASE into a directory named $EXPORTDIR/flashrom-$VERSION-r$SVNREVISION
and will additionally modify the Makefile in that directory to contain the svn
revision of the exported tree.
make tarball will simply tar up the result of make export and gzip compress it.
The snapshot tarballs are the result of make tarball and require no further
processing.
Build Instructions
------------------
To build flashrom you need to install the following packages or ports:
Linux et al:
* pciutils
* pciutils-devel / pciutils-dev / libpci-dev
* zlib-devel / zlib1g-dev
On FreeBSD, you need the following ports:
* devel/gmake
* devel/libpci
To compile on Linux, use:
make
To compile on FreeBSD, use:
gmake
To compile on Solaris, use:
gmake LDFLAGS="-L$pathtolibpci -lpci -lz" CC="gcc -I$pathtopciheaders" \
CFLAGS=-O2
To compile on DragonFly BSD, use:
ln -s /usr/pkg/include/pciutils pci
gmake CFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -lpci -lz"
To compile and run on Darwin/Mac OS X:
Install DirectIO from coresystems GmbH.
DirectIO is available at http://www.coresystems.de/en/directio.
Installation
------------
In order to install flashrom and the manpage into /usr/local, type:
sudo make install
For installation in a different directory use DESTDIR, e.g. like this:
sudo make DESTDIR=/usr install
Usage / Options
---------------
Please see the flashrom(8) manpage.
Exit status
-----------
Please see the flashrom(8) manpage.
coreboot Table and Mainboard Identification
--------------------------------------------
Please see the flashrom(8) manpage.
ROM Layout Support
------------------
Please see the flashrom(8) manpage.
Supported Flash Chips / Chipsets / Mainboards
---------------------------------------------
Please check the output of 'flashrom -L' for the list of supported
flash chips, chipsets/southbridges, mainboards, and flash programmers.
Website
-------
The official flashrom website is:
http://coreboot.org/Flashrom