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Code Issues Releases Wiki Activity

Add RISCV vector extension (#289)

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Co-authored-by: Michael Roe <michael-roe@users.noreply.github.com>
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michael-roe
2023-04-24 14:36:22 +01:00
committed by GitHub
parent 5607a689e0
commit 75ec988188
4 changed files with 28 additions and 0 deletions
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2
include/cpuinfo_riscv.h
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@ -36,6 +36,7 @@ typedef struct {
int D : 1; // Standard Extension for Double-Precision Floating-Point
int Q : 1; // Standard Extension for Quad-Precision Floating-Point
int C : 1; // Standard Extension for Compressed Instructions
int V : 1; // Standard Extension for Vector Instructions
int Zicsr : 1; // Control and Status Register (CSR)
int Zifencei : 1; // Instruction-Fetch Fence
} RiscvFeatures;
@ -55,6 +56,7 @@ typedef enum {
RISCV_D,
RISCV_Q,
RISCV_C,
RISCV_V,
RISCV_Zicsr,
RISCV_Zifencei,
RISCV_LAST_,

1
include/internal/hwcaps.h
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@ -214,6 +214,7 @@ CPU_FEATURES_START_CPP_NAMESPACE
#define RISCV_HWCAP_D (1UL << ('D' - 'A'))
#define RISCV_HWCAP_Q (1UL << ('Q' - 'A'))
#define RISCV_HWCAP_C (1UL << ('C' - 'A'))
#define RISCV_HWCAP_V (1UL << ('V' - 'A'))
typedef struct {
unsigned long hwcaps;