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mirror of https://github.com/google/cpu_features.git synced 2025-04-27 15:12:30 +02:00

48 Commits

Author SHA1 Message Date
Christian Clauss
dcddc4a2cb Fix typos discovered by codespell 2025-02-26 13:37:34 +01:00
Guillaume Chatelet
8cfb520efb [NFC] clang-format the code base 2023-09-25 07:35:53 +00:00
Mykola Hohsadze
312e990c6f
Add Intel AMX-FP16 detection (#332) 2023-09-14 10:22:16 +02:00
Tomahawkd
b5cb91b35c
Add Intel LAM/AMD UAI feature detection in X86_64 (#315)
* Add Intel LAM/AMD UAI features in X86

* Add AMD UAI test for AMD_K19_ZEN4_RAPHAEL

* Add separate UAI for AMD
2023-08-28 16:25:24 +02:00
Mykola Hohsadze
c74a85d64a
Add documentation on current behavior for X86 (#212)
* Add documentation for X86 OS support

* Update X86 documentation

* Remove outdated cache info comment

* Update x86 documentation according to comments

* Update Internal structures documentation
2023-01-24 20:27:10 +01:00
Mykola Hohsadze
19799486d2
Add Intel Raptor Lake uarch detection (#283) 2022-11-08 15:35:50 +01:00
Mykola Hohsadze
bddcc3721c
Add REP instructions detection (#282) 2022-10-26 16:13:15 +02:00
Mykola Hohsadze
26852665b4
Add X86 movdir detection (#281) 2022-10-25 09:33:13 +02:00
Mykola Hohsdze
3485a46a6d Add X86 GFNI detection 2022-10-24 08:29:55 +02:00
damageboy
8ca7c65f65
add x86/avx512_fp16 detection (#279)
fixes #278
2022-10-20 11:26:13 +02:00
William Tambellini
b69591add3
Add support for detecting Intel CascadeLake CPUs (#271)
Should close
https://github.com/google/cpu_features/issues/260
2022-09-19 10:00:01 +02:00
Andrei Kurushin
4e8d2e3a22
add intel goldmont plus (#256)
* add intel goldmont plus (INTEL_ATOM_GMT_PLUS)
2022-08-08 09:27:18 +02:00
Daniele Affinita
426b036e8d
Added some missing amd k12 uarch (#259)
* Add comment about AMD_K12 LLANO.
* Add family 0x12 model 0x00 to it.
2022-08-04 22:30:46 +02:00
Mykola Hohsdze
c6b0a803a8 Add AVX_VNNI 2022-08-04 21:56:32 +02:00
Andrew Kurushin
6d62f2fa64 add intel Tremont microarch 2022-08-04 21:54:23 +02:00
Mykola Hohsadze
601471d527
Add detection LZCNT (#254)
Fixes #253
2022-07-28 12:22:16 +02:00
Andrei Kurushin
8eb944f55d
add comet lake support #248 (#249) 2022-07-13 10:28:34 +02:00
Guillaume Chatelet
db9ad9fc2c Add not about avx512_4vbmi2 being an alias of avx512_4fmaps 2022-07-12 15:45:51 +00:00
Mykola Hohsadze
3c4801d12d
Add AMD ZEN 4 uarch and update detection (#243)
* Add AMD ZEN 4 uarch and update detection

* Add tests via cpuid dump
2022-06-17 11:18:05 +02:00
AnvilaWang
1d02169588
Add support for ZHAOXIN CPU (#218) 2022-02-18 16:32:06 +01:00
Guillaume Chatelet
149916384b
[x86] Embed brand_string and mark FillX86BrandString as deprecated (#214) 2022-01-14 17:20:31 +01:00
Nikolay Hohsadze
5695cc4817
Update uarch detection for Intel processors (#184) 2021-10-29 10:41:50 +02:00
Guillaume Chatelet
f96d5f74d4 NFC remove reference to libc memory functions 2021-10-28 11:56:57 +00:00
Guillaume Chatelet
deb2a61b80
New code layout - breaking change in cpu_features_macros.h (#194)
This commit helps with platform code separation (fixes #3). It should also help with the build as we can simply include all `impl_*.c` files regardless of OS / arch.

Note: this patch contains breaking changes in `include/cpu_features_macros.h`
 - `CPU_FEATURES_OS_LINUX_OR_ANDROID` does not exist anymore
 - `CPU_FEATURES_OS_FREEBSD`, `CPU_FEATURES_OS_ANDROID` and `CPU_FEATURES_OS_LINUX` are now mutually exclusive (i.e. `CPU_FEATURES_OS_ANDROID` does not imply `CPU_FEATURES_OS_LINUX`)
 - `CPU_FEATURES_OS_DARWIN` has been renamed into `CPU_FEATURES_OS_MACOS` to be able to target non-Mac Apple products (IOS, TV, WATCH). They are now targetable with `CPU_FEATURES_OS_IPHONE`. This matches Apple naming convention described in [this stackoverflow](https://stackoverflow.com/a/49560690).
2021-10-28 13:52:46 +02:00
Nikolay Hohsadze
0925f6953c
Add cache info for new AMD CPUs (0x8000001D) (#171) 2021-10-18 14:14:29 +02:00
Nikolay Hohsadze
5492c4c561
CPU features for AMD (#165) 2021-06-30 12:38:56 +02:00
Kris Kwiatkowski
d35e2f38eb
Detect Intel's Multi-Precision Add-Carry Instruction Extensions (#157) 2021-05-21 10:47:32 +02:00
natanbc
7ed0b0e50e
Detect Zen 3 (K19) cpus (#152)
Co-authored-by: natanbc <natanbc@users.noreply.github.com>
2021-02-25 21:47:39 +01:00
Guillaume Chatelet
3cc8f310d9 [NFC] Update copyright from Google Inc. to Google LLC 2020-10-12 08:55:20 +00:00
Jeff Hammond
17ffb65117
detect AVX-512 FMA count (#125)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* second FMA features - incomplete and wrong

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* oops: use T/F not 2/1

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* implement SKX lookup

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

* cleanup AVX512 second FMA code

1) remove debug stuff
2) remove ICX - will add details when available

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* fix CPX detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove elses

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove curly braces from single-line conditional bodies

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* apply clang-format

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

Fixes #120
2020-09-22 07:29:46 +00:00
Jeff Hammond
33bd72c1bc
detect future Intel AVX/AMX features (#124)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AVX512_BF16 and AVX512_VP2INTERSECT detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* correction for KNM features: s/4VBMI2/4FMAPS/g

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AMX/TMUL bits from 319433-040

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fixes #128
2020-09-21 07:56:26 +00:00
Jeff Hammond
e698327713
add future Intel microarchitectures (#123)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fix #127
2020-09-21 07:54:58 +00:00
gadoofou87
3262a55118 Support x86 FMA4 and SSE4A features 2020-03-12 10:58:41 +00:00
Moxeja
73a121b1ae Differentiate between different Lake uarch 2020-01-06 16:23:29 +01:00
Artem Alekseev
653d581e03 Add support for leaf2 and leaf4 on Intel's x86 arch (#80)
* Add support for leaf4 on Intel's x86 arch
* Update cpuinfo_x86.h
* Fix typo
* Force compiler to use C99
* Add Intel x86 leaf2 support
* Fixes after review
* Fix review comments
2019-07-02 16:52:25 +02:00
Artem Alekseev
3ee4a9e801 Support x86 DCA and SS features (#76)
* Add dca and ss features
* Remove trailing white spaces
2019-06-19 15:06:05 +02:00
Dr.-Ing. Patrick Siegl
367bc42116 Support x86 features: FPU, TSC, CX8, CLFSH, MMX, VAES, HLE, RTM, RDSEED, CLFLUSHOPT, CLWB, SSE, SSE2, SSE3, PCLMULQDQ (#73) 2019-06-13 11:53:39 +02:00
Guillaume Chatelet
d395dfa026
Add x86 missing feature detections for ndk_compat (#58)
One more step towards #47.
2019-01-22 13:19:42 +01:00
Guillaume Chatelet
4155ee7e36
Guarding header use with architecture (#56) 2019-01-18 13:38:22 +01:00
Guillaume Chatelet
9b872ce0b2 Add cx16 (cmpxchg16b) cpuid flag. Fixes #30 2018-03-13 10:58:42 +01:00
Patrik Fiedler
3ee0d62e87
detect intel sgx and smx cpu features for the x86 arch 2018-02-13 11:16:48 +01:00
Guillaume Chatelet
e419573d10 Use CPU_FEATURES_ prefix for namespace macros. 2018-02-12 16:15:15 +01:00
Guillaume Chatelet
11e3e20496 Reverting 338484f6f2176c3d8ede0ed2f3fbd6cf1eb0274c. Fixes #2 2018-02-09 08:55:11 +01:00
Guillaume Chatelet
1d6ba6139c
Merge pull request #5 from bsurmanski/patch-1
Fix spelling mistake for 'Cannon Lake'
2018-02-08 16:34:15 +01:00
Guillaume Chatelet
338484f6f2 Fixes #2 - vpclmulqdq should be pclmulqdq. 2018-02-08 11:35:31 +01:00
Brandon Surmanski
efcc49a493
Fix spelling mistake for 'Cannon Lake'
See:
https://www.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/platform-codenames.html
https://en.wikipedia.org/wiki/Cannon_Lake_(microarchitecture)
2018-02-07 11:07:00 -08:00
Guillaume Chatelet
8e58ef0d2b Removing THIRD_PARTY_ from C headers. 2018-02-01 10:38:48 +01:00
Guillaume Chatelet
439d371594 Adding code. Closes #0. 2018-02-01 10:03:09 +01:00