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mirror of https://github.com/google/cpu_features.git synced 2025-04-27 15:12:30 +02:00

95 Commits

Author SHA1 Message Date
Guillaume Chatelet
149916384b
[x86] Embed brand_string and mark FillX86BrandString as deprecated (#214) 2022-01-14 17:20:31 +01:00
Nikolay Hohsadze
5695cc4817
Update uarch detection for Intel processors (#184) 2021-10-29 10:41:50 +02:00
Guillaume Chatelet
deb2a61b80
New code layout - breaking change in cpu_features_macros.h (#194)
This commit helps with platform code separation (fixes #3). It should also help with the build as we can simply include all `impl_*.c` files regardless of OS / arch.

Note: this patch contains breaking changes in `include/cpu_features_macros.h`
 - `CPU_FEATURES_OS_LINUX_OR_ANDROID` does not exist anymore
 - `CPU_FEATURES_OS_FREEBSD`, `CPU_FEATURES_OS_ANDROID` and `CPU_FEATURES_OS_LINUX` are now mutually exclusive (i.e. `CPU_FEATURES_OS_ANDROID` does not imply `CPU_FEATURES_OS_LINUX`)
 - `CPU_FEATURES_OS_DARWIN` has been renamed into `CPU_FEATURES_OS_MACOS` to be able to target non-Mac Apple products (IOS, TV, WATCH). They are now targetable with `CPU_FEATURES_OS_IPHONE`. This matches Apple naming convention described in [this stackoverflow](https://stackoverflow.com/a/49560690).
2021-10-28 13:52:46 +02:00
Guillaume Chatelet
32b49eb5e7
Fixes wrong cache detection of old processors (#183) 2021-10-20 17:02:52 +02:00
Guillaume Chatelet
4a81f3756e [NFC] encapsulate fake cpu instance in x86 test 2021-10-20 08:15:44 +00:00
Nikolay Hohsadze
0925f6953c
Add cache info for new AMD CPUs (0x8000001D) (#171) 2021-10-18 14:14:29 +02:00
Guillaume Chatelet
f70dc46cd5
Add separator to CpuFeatures_StringView_HasWord (#174) 2021-10-18 12:52:14 +02:00
Guillaume Chatelet
119943707c
Add support for FreeBSD on x86 (#163) 2021-07-02 15:37:03 +02:00
Nikolay Hohsadze
5492c4c561
CPU features for AMD (#165) 2021-06-30 12:38:56 +02:00
Guillaume Chatelet
b3ef4ef49d
Avoid leaking internal headers for ppc (#164) 2021-06-30 11:51:26 +02:00
Kris Kwiatkowski
d35e2f38eb
Detect Intel's Multi-Precision Add-Carry Instruction Extensions (#157) 2021-05-21 10:47:32 +02:00
Tamas Zsoldos
e2f6dea65f
Update AArch64 features to Linux 5.10 (#149)
Added feature: MTE.
2020-12-15 13:28:53 +01:00
Guillaume Chatelet
9a8f04b24c
[NFC] Generate separate tables via macro (#137)
This is a non functional change, it allows:
 - Getting rid of `unix_features_aggregator`
 - Have a single blob describing the features
 - Fix wrong mocking of `hwcaps`

Downside: abuse of macros makes the code slightly magical and harder to understand.
It think it's still an improvement over the current situation as there's less repetition and less chances to get something wrong.
2020-10-12 09:50:35 +00:00
Guillaume Chatelet
3cc8f310d9 [NFC] Update copyright from Google Inc. to Google LLC 2020-10-12 08:55:20 +00:00
Guillaume Chatelet
e63405f118
Remove need for utsname (#136) 2020-10-09 20:40:06 +00:00
Guillaume Chatelet
4795373db2
Fix SSE detection on non-AVX CPUs (#135)
Fixes #4. This is based on #115 with a few modifications:
 - Removed use of __builtin_cpu_supports since it relies on cpuid and doesn't improve on the current situation,
 - Added detection for all of sse, sse2, sse3, ssse3, sse4_1 and sse4_2,
 - Added tests for Atom, Nehalem, and P3 processors,

Thx to @gadoofou87 for providing the original PR.
It also removes the need for #92

* Fix SSE detection on non-AVX CPUs
* Fixes typo
* Mock OSX sysctlbyname in tests
* Also update other tests
* FakeCpu is reset between each tests
* Fix conflicting name on Windows
* Disable pre AVX cpu sse detection tests on Windows
* Guard OS specific code with macros
* Fix missing import for tests
* Fix wrong function prototype
* Fix wrong mocking of P3 on Windows
* Completely guard OS specific parts in x86 tests
* Store DWORD instead unsigned long for x86 tests
2020-10-09 15:20:25 +00:00
Guillaume Chatelet
22a5362e11
[NFC] clang-format codebase (#134)
* [NFC] clang-format codebase

* revert to 80 char columns at the price of uglier table init

* Specifically disabling clang-format for table initialization
2020-09-23 09:52:20 +00:00
Jeff Hammond
33bd72c1bc
detect future Intel AVX/AMX features (#124)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AVX512_BF16 and AVX512_VP2INTERSECT detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* correction for KNM features: s/4VBMI2/4FMAPS/g

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AMX/TMUL bits from 319433-040

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fixes #128
2020-09-21 07:56:26 +00:00
Tamas Zsoldos
73d10ad25b
Update features for AArch64 to Linux 5.8 (#122)
This adds the following features: dcpodp, sve2, sveaes, svepmull,
svebitperm, svesha3, svesm4, flagm2, frint, svei8mm, svef32mm,
svef64mm, svebf16, i8mm, bf16, dgh and rng.

With these, all features used by Linux 5.8 on AArch64 is supported.

Fixes #126
2020-09-21 07:50:38 +00:00
Henry Lee
9e03e13ae7
Add more test cases for the string view (#119) 2020-09-21 07:39:58 +00:00
Nikita Karpey
ba81cb3da9
CMake: Enable CXX compiler for tests only (#110)
CMake: Enable CXX compiler for tests only

Co-authored-by: Mizux <mizux.dev@gmail.com>
2020-03-11 14:40:23 +01:00
Patrick Siegl
3d71a964f5 Use a getter function to avoid manual work for future to-be-added cpu features 2020-01-06 16:24:10 +01:00
Tamas Zsoldos
d835b4958c Update features for AArch64.
Add all missing features up to Linux v5.0.

Features added: evtstrm, atomics, fphp, asimdhp, cpuid, asimdrdm,
jscvt, fcma, lrcpc, dcpop, sha3, sm3, sm4, asimddp, sha512, sve,
asimdfhm, dit, uscat, ilrcpc, flagm, ssbs, sb, paca, pacg.
2019-10-11 11:02:00 +02:00
Leonard Mosescu
bdb36d9489 Fix a few compile warnings (#84)
Visual C++ reported a number of warnings:

..\src\filesystem.c(27): warning C4996: '_open': This function or variable may be unsafe. Consider using _sopen_s instead. To disable deprecation, use _CRT_SECURE_NO_WARNINGS. See online help for details.
..\src\filesystem.c(34): warning C4267: 'function': conversion from 'size_t' to 'unsigned int', possible loss of data
..\src\string_view.c(25): warning C4244: 'return': conversion from '__int64' to 'int', possible loss of data
..\src\string_view.c(41): warning C4244: 'return': conversion from '__int64' to 'int', possible loss of data
..\src\utils\list_cpu_features.c(151): warning C4090: 'function': different 'const' qualifiers
..\src\cpuinfo_x86.c(67): warning C4244: 'return': conversion from 'unsigned __int64' to 'uint32_t', possible loss of data
..\test\filesystem_for_testing.cc(48): warning C4267: 'return': conversion from 'size_t' to 'int', possible loss of data
..\test\filesystem_for_testing.cc(57): warning C4267: 'argument': conversion from 'size_t' to 'int', possible loss of data
..\test\bit_utils_test.cc(26): warning C4267: 'argument': conversion from 'size_t' to 'uint32_t', possible loss of data
..\test\bit_utils_test.cc(32): warning C4267: 'argument': conversion from 'size_t' to 'uint32_t', possible loss of data
..\test\bit_utils_test.cc(37): warning C4267: 'argument': conversion from 'size_t' to 'uint32_t', possible loss of data

Most of them, with the exception of _open() -> _sopen_s() are about
questionable implicit casts. Fixing the types and adding explicit casts
to explicitly mark the intention (and silence the warnings in the process)
2019-07-03 14:57:19 +02:00
Artem Alekseev
653d581e03 Add support for leaf2 and leaf4 on Intel's x86 arch (#80)
* Add support for leaf4 on Intel's x86 arch
* Update cpuinfo_x86.h
* Fix typo
* Force compiler to use C99
* Add Intel x86 leaf2 support
* Fixes after review
* Fix review comments
2019-07-02 16:52:25 +02:00
Dr.-Ing. Patrick Siegl
bfd109b687 Completed all missing ARM hwcaps. (#79) 2019-06-26 12:56:52 +02:00
Dr.-Ing. Patrick Siegl
18342789a1 Fix ARMv6 on Linux vs Android (#81) 2019-06-25 17:58:31 +02:00
Artem Alekseev
bfb4cf99cc Add CpuIdEx function to pass inputs in ecx register (required for E.g. leaf4) (#77) 2019-06-21 14:13:29 +02:00
Dr.-Ing. Patrick Siegl
6482bad213 Added RPI zero with its features HALF, THUMB, FASTMULT, EDSP, JAVA and TLS (#75) 2019-06-18 12:53:08 +02:00
Guillaume Chatelet
d395dfa026
Add x86 missing feature detections for ndk_compat (#58)
One more step towards #47.
2019-01-22 13:19:42 +01:00
Guillaume Chatelet
5911e96bbd
add r6 flag (#57)
Update tests and add support in ndk-compat as well
2019-01-22 11:00:48 +01:00
Guillaume Chatelet
9917e8481e
Fix hwcaps constants for mips. (#60)
fixes #59
2019-01-21 10:39:24 +01:00
Guillaume Chatelet
4155ee7e36
Guarding header use with architecture (#56) 2019-01-18 13:38:22 +01:00
Guillaume Chatelet
dfdac6adfc
Add partial implementation of ndk_compat (#54)
* First implementation of ndk_compat
* Restrict building of linux_based_hardware_detection to UNIX
* Fix variable declaration and printf formatting
* Restrict ndk compat to UNIX style systems
* Restrict cpu_mask index to 32
* Fix values display in ndk-compat-test
* Addressing comments
2019-01-17 18:00:21 +01:00
Guillaume Chatelet
918553a21f Export GetArmCpuId function 2019-01-17 15:28:04 +01:00
Guillaume Chatelet
122b067087 Use Cmake macros to detect getauxval and dlopen 2019-01-15 15:18:08 +01:00
Guillaume Chatelet
e8e5610fc4 Per arch build and inlining of cpuid_x86. 2019-01-15 10:52:56 +01:00
Guillaume Chatelet
26133d3b62 Match function definition and declaration arguments. 2018-06-20 09:18:57 +02:00
Rashmica Gupta
c45e32f812
powerpc: Add AT_PLATFORM and AT_BASE_PLATFORM
Some PowerPC machines can operate in a mode that appears different
to a process than the actual hardware. AT_PLATFORM indicates the
supported instruction set and AT_BASE_PLATFORM indicates the
actual microarchitecture of the hardware.

Signed-off-by: Rashmica Gupta <rashmica.gupta@au1.ibm.com>
2018-05-15 14:24:58 +10:00
Rashmica Gupta
3adafbfe66
powerpc: Added PowerPC implementation
Signed-off-by: Rashmica Gupta <rashmica.gupta@au1.ibm.com>
2018-05-15 14:24:45 +10:00
Arvid Gerstmann
d968991caa Reformat files 2018-05-04 09:32:17 +02:00
Arvid Gerstmann
fd4839032c Fix tests & fix missing GetHardwareCapabilities() change 2018-05-03 17:07:07 +02:00
Guillaume Chatelet
9f3b0241aa Fix typo in test makefile. 2018-02-08 17:08:52 +01:00
Guillaume Chatelet
8e58ef0d2b Removing THIRD_PARTY_ from C headers. 2018-02-01 10:38:48 +01:00
Guillaume Chatelet
439d371594 Adding code. Closes #0. 2018-02-01 10:03:09 +01:00