1
0
mirror of https://github.com/google/cpu_features.git synced 2025-04-28 23:43:37 +02:00

124 Commits

Author SHA1 Message Date
Mykola Hohsadze
627959faee
Add AMD ZEN4 Raphael detection (#277) 2022-10-19 11:36:27 +02:00
Andrei Kurushin
4760834428
add mobile core flavor (#266) 2022-10-19 11:35:19 +02:00
William Tambellini
b69591add3
Add support for detecting Intel CascadeLake CPUs (#271)
Should close
https://github.com/google/cpu_features/issues/260
2022-09-19 10:00:01 +02:00
Mykola Hohsadze
cee2648cf0
Add cache detection for old AMD processors (#199)
* Add cache detection for of old AMD processors




update links

* Add documentation link for cache_size * 512

* Update legacy amd cache detection
2022-08-18 13:55:21 +02:00
Andrei Kurushin
1e253a7728
add amd cato (#267)
* add AMD RX-8125, RX-8120, and A9-9820 detection
2022-08-18 10:40:24 +02:00
Mykola Hohsadze
cd97c7cee7
Get rid repeated branch (#269)
* Get rid repeated branch
* Update cache type field comment
2022-08-18 10:39:00 +02:00
Andrei Kurushin
4e8d2e3a22
add intel goldmont plus (#256)
* add intel goldmont plus (INTEL_ATOM_GMT_PLUS)
2022-08-08 09:27:18 +02:00
Andrei Kurushin
876b9e6a73
add amd piledriver 0x10 model (#255)
* add amd piledriver 0x10 model
2022-08-05 15:56:53 +02:00
Andrew Kurushin
349ef06634 add CometLake model 166 2022-08-05 15:55:18 +02:00
Daniele Affinita
426b036e8d
Added some missing amd k12 uarch (#259)
* Add comment about AMD_K12 LLANO.
* Add family 0x12 model 0x00 to it.
2022-08-04 22:30:46 +02:00
Mykola Hohsdze
c6b0a803a8 Add AVX_VNNI 2022-08-04 21:56:32 +02:00
Andrew Kurushin
cbc8f9c7a3 add Lakefield 2022-08-04 21:54:23 +02:00
Andrew Kurushin
6d62f2fa64 add intel Tremont microarch 2022-08-04 21:54:23 +02:00
Guillaume Chatelet
f60b6f8405 [NFC] Remove unused variable 2022-07-28 14:29:50 +00:00
Mykola Hohsadze
601471d527
Add detection LZCNT (#254)
Fixes #253
2022-07-28 12:22:16 +02:00
Andrei Kurushin
677d6419b2
remove internal FillX86BrandString usage (#258) 2022-07-25 17:39:50 +02:00
Andrei Kurushin
38ae5d095c
add windows ssse3,sse4_1,sse4_2 detection for non avx path (#251)
* add windows ssse3,sse4_1,sse4_2 detection for non avx path

* remove special WESTMERE case

* move windows conditional redefinition to separate header

* fix minor issues
2022-07-21 21:56:50 +02:00
Andrei Kurushin
8eb944f55d
add comet lake support #248 (#249) 2022-07-13 10:28:34 +02:00
Mykola Hohsadze
3c4801d12d
Add AMD ZEN 4 uarch and update detection (#243)
* Add AMD ZEN 4 uarch and update detection

* Add tests via cpuid dump
2022-06-17 11:18:05 +02:00
michael-roe
08f2dc115e
Added some MIPS features. (#241)
Co-authored-by: Michael Roe <michael-roe@users.noreply.github.com>
2022-06-01 15:58:29 +02:00
Tamas Zsoldos
b04a9daf71
Update AArch64 features to Linux 5.17. (#237) 2022-04-27 10:26:29 +02:00
Guillaume Chatelet
7fe96b1d3d
Comply with -Wstrict-prototypes 2022-04-14 11:01:06 +02:00
Guillaume Chatelet
dedea3a5a7
Comply with -Wstrict-prototypes 2022-04-13 13:21:32 +02:00
jmfriedt
40e1c7158d
replace sse3 detection with pni when reading /proc/cpuinfo (#225) 2022-02-22 14:19:17 +01:00
AnvilaWang
1d02169588
Add support for ZHAOXIN CPU (#218) 2022-02-18 16:32:06 +01:00
Ryan Prichard
5f5e6d620f
Fix a getauxval comment and expand the Krait idiv workaround (#206)
* Fix getauxval comment (API 18 not 20)

getauxval is available in Android starting with API 18, not 20.

The comment about __ANDROID_API__ appears to have been copied from the
NDK's cpufeatures, which always uses dlopen/dlsym and doesn't assume it
can directly call getauxval, even if __ANDROID_API__ is new enough.
With this project, though, when __ANDROID_API__ is 18 or up, the
CMakeLists.txt file would detect that getauxval is available and define
HAVE_STRONG_GETAUXVAL.

* Broaden Qualcomm Krait idiv workaround

Some Qualcomm Krait CPUs have IDIV support but the kernel doesn't
report it. Previously, this code looked for two CPUs:
 - 0x510006F2 (0x51/'Q', variant 0, part 0x06f, rev 2)
 - 0x510006F3 (0x51/'Q', variant 0, part 0x06f, rev 3)

This check misses my 2013 Nexus 7 device, which has this CPU ID:
 - 0x511006f0 (0x51/'Q', variant 1, part 0x06f, rev 0)

My Nexus 7 device doesn't report idiv through AT_HWCAP or through
/proc/cpuinfo (AT_HWCAP is 0x1b0d7).

Expand the check to anything with:
 - implementer 0x51
 - architecture 7
 - part 0x4d or 0x6f

Part 0x4d appears to be a dual-core Krait (e.g. see
https://crbug.com/341598#c43).

This new matching behavior is a subset of what the upstream kernel
does (patch[1] contributed by CodeAurora), and also closely matches the
behavior of pytorch/cpuinfo.

[1] 120ecfafab
2022-02-01 17:25:05 +01:00
Mykola Hohsadze
f1801f0ca1
Fix list_cpu_features.exe does not detect SSE42 on Xeon X5650 (Windows) (#220) 2022-01-31 10:15:17 +01:00
Guillaume Chatelet
149916384b
[x86] Embed brand_string and mark FillX86BrandString as deprecated (#214) 2022-01-14 17:20:31 +01:00
Guillaume Chatelet
aa642e573e [NFC] Avoid polluting global scope 2022-01-14 16:06:30 +00:00
Guillaume Chatelet
5ed8ef4bbe
[NFC][x86] Read all cpuid leaves at once (#213)
This patch reads the most important cpuid leaves and stores the data in
a struct. A followup patch will inline micro architecture detection and
brand string inside X86Info so we don't have to call `ReadLeaves` multiple
times. This wil allow further simplification of `HasSecondFMA` and help
fix https://github.com/google/cpu_features/issues/200.
2022-01-14 14:14:07 +01:00
Guillaume Chatelet
9d34e6a1c8 Fix #205
Since buffers are a few tens of bytes there is no need for optimized memfunctions. For compile time sizes, the compiler will generate optimal code already.
2021-11-22 16:50:29 +00:00
Guillaume Chatelet
ebcdfcaeff Fix missing header 2021-10-29 13:54:41 +00:00
Guillaume Chatelet
f69a25811f make copy and equals inline headers 2021-10-29 12:41:43 +00:00
Guillaume Chatelet
990c55c50f Silence unsused parameters 2021-10-29 10:48:52 +00:00
Guillaume Chatelet
6fd9a8ca58 Make getter/setter static so they don't leak 2021-10-29 10:47:01 +00:00
Guillaume Chatelet
400d4f2836 Fix CpuFeatures_memchr to actually use the provided size argument 2021-10-29 10:10:20 +00:00
Nikolay Hohsadze
5695cc4817
Update uarch detection for Intel processors (#184) 2021-10-29 10:41:50 +02:00
Guillaume Chatelet
deb2a61b80
New code layout - breaking change in cpu_features_macros.h (#194)
This commit helps with platform code separation (fixes #3). It should also help with the build as we can simply include all `impl_*.c` files regardless of OS / arch.

Note: this patch contains breaking changes in `include/cpu_features_macros.h`
 - `CPU_FEATURES_OS_LINUX_OR_ANDROID` does not exist anymore
 - `CPU_FEATURES_OS_FREEBSD`, `CPU_FEATURES_OS_ANDROID` and `CPU_FEATURES_OS_LINUX` are now mutually exclusive (i.e. `CPU_FEATURES_OS_ANDROID` does not imply `CPU_FEATURES_OS_LINUX`)
 - `CPU_FEATURES_OS_DARWIN` has been renamed into `CPU_FEATURES_OS_MACOS` to be able to target non-Mac Apple products (IOS, TV, WATCH). They are now targetable with `CPU_FEATURES_OS_IPHONE`. This matches Apple naming convention described in [this stackoverflow](https://stackoverflow.com/a/49560690).
2021-10-28 13:52:46 +02:00
Guillaume Chatelet
c5659bf16f Override CacheInfo only if new data is available via Deterministic Cache Parameters Leaf
#190
2021-10-26 15:21:27 +00:00
Guillaume Chatelet
7bd206a75f Fix memory overflow
Duplicate of #190
2021-10-26 13:58:42 +00:00
Guillaume Chatelet
769287c384
Fixes #185 (#187)
Missing `string_view` header and invalid `_Static_assert` statement
2021-10-25 09:48:46 +02:00
Guillaume Chatelet
cf589a2844
[NFC] Change implementation of FillX86BrandString (#181) 2021-10-21 10:51:00 +02:00
Guillaume Chatelet
32b49eb5e7
Fixes wrong cache detection of old processors (#183) 2021-10-20 17:02:52 +02:00
Nikolay Hohsadze
0925f6953c
Add cache info for new AMD CPUs (0x8000001D) (#171) 2021-10-18 14:14:29 +02:00
Guillaume Chatelet
f70dc46cd5
Add separator to CpuFeatures_StringView_HasWord (#174) 2021-10-18 12:52:14 +02:00
Guillaume Chatelet
119943707c
Add support for FreeBSD on x86 (#163) 2021-07-02 15:37:03 +02:00
Nikolay Hohsadze
5492c4c561
CPU features for AMD (#165) 2021-06-30 12:38:56 +02:00
Guillaume Chatelet
b3ef4ef49d
Avoid leaking internal headers for ppc (#164) 2021-06-30 11:51:26 +02:00
Kris Kwiatkowski
001faefdc3
fix: Return default value from ‘GetCacheTypeString’ (#162)
The build fails with following message when -Werror
and -Werror=return-type are enabled.

In function ‘GetCacheTypeString’:
	error: control reaches end of non-void function [-Werror=return-type]

Simple fix is to return explicitly communicate to
the compiler that certain block is not reachable.
2021-06-25 10:28:26 +02:00
Guillaume Chatelet
646b80fa3a
[NFC] refactor the code so it's easier to understand the execution flow (#161) 2021-06-23 14:21:05 +00:00