mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-26 22:52:34 +02:00
Unify PCI init and let pcidev clean itself up
Previously the internal programmer used its own code to initialize pcilib. This patch extracts the common code from the internal programmer and pcidev_init() into pcidev_init_common(). This fixes the non-existent PCI cleanup of the internal programmer and adds an additional safety by checking for an already existing PCI context. We got a nice shutdown function registration infrastructure, but did not use it very wisely. Instead we added shutdown functions to a myriad of programmers unnecessarily. In this patch we get rid of those that do only call pci_cleanup(pacc) by adding a shutdown function the pcidev.c itself that gets registered by pcidev_init(). Corresponding to flashrom svn r1642. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
parent
30dfdbaf3a
commit
5561955b11
10
atahpt.c
10
atahpt.c
@ -56,13 +56,6 @@ static const struct par_programmer par_programmer_atahpt = {
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.chip_writen = fallback_chip_writen,
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};
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static int atahpt_shutdown(void *data)
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{
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/* Flash access is disabled automatically by PCI restore. */
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pci_cleanup(pacc);
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return 0;
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}
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int atahpt_init(void)
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{
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uint32_t reg32;
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@ -72,9 +65,6 @@ int atahpt_init(void)
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io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt);
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if (register_shutdown(atahpt_shutdown, NULL))
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return 1;
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/* Enable flash access. */
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reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS);
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reg32 |= (1 << 24);
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@ -59,8 +59,6 @@ static const struct par_programmer par_programmer_drkaiser = {
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static int drkaiser_shutdown(void *data)
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{
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physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE);
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/* Flash write is disabled automatically by PCI restore. */
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pci_cleanup(pacc);
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return 0;
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}
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@ -71,6 +69,7 @@ int drkaiser_init(void)
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if (rget_io_perms())
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return 1;
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/* No need to check for errors, pcidev_init() will not return in case of errors. */
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addr = pcidev_init(PCI_BASE_ADDRESS_2, drkaiser_pcidev);
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/* Write magic register to enable flash write. */
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@ -80,10 +80,6 @@ static const struct par_programmer par_programmer_gfxnvidia = {
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static int gfxnvidia_shutdown(void *data)
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{
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physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE);
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/* Flash interface access is disabled (and screen enabled) automatically
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* by PCI restore.
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*/
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pci_cleanup(pacc);
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return 0;
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}
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@ -94,6 +90,7 @@ int gfxnvidia_init(void)
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if (rget_io_perms())
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return 1;
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/* No need to check for errors, pcidev_init() will not return in case of errors. */
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io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia);
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io_base_addr += 0x300000;
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@ -101,7 +98,6 @@ int gfxnvidia_init(void)
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nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE);
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/* Must be done before rpci calls. */
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if (register_shutdown(gfxnvidia_shutdown, NULL))
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return 1;
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@ -245,10 +245,8 @@ int internal_init(void)
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internal_buses_supported = BUS_NONSPI;
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/* Initialize PCI access for flash enables */
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pacc = pci_alloc(); /* Get the pci_access structure */
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/* Set all options you want -- here we stick with the defaults */
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pci_init(pacc); /* Initialize the PCI library */
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pci_scan_bus(pacc); /* We want to get the list of devices */
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if (pci_init_common() != 0)
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return 1;
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if (processor_flash_enable()) {
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msg_perr("Processor detection/init failed.\n"
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@ -81,7 +81,6 @@ static int nic3com_shutdown(void *data)
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OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
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}
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pci_cleanup(pacc);
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return 0;
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}
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@ -90,6 +89,7 @@ int nic3com_init(void)
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if (rget_io_perms())
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return 1;
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/* No need to check for errors, pcidev_init() will not return in case of errors. */
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io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_3com);
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id = pcidev_dev->device_id;
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@ -63,7 +63,6 @@ static int nicintel_shutdown(void *data)
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{
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physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE);
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physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE);
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pci_cleanup(pacc);
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return 0;
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}
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@ -77,8 +76,7 @@ int nicintel_init(void)
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if (rget_io_perms())
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return 1;
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/* No need to check for errors, pcidev_init() will not return in case
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* of errors.
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/* No need to check for errors, pcidev_init() will not return in case of errors.
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* FIXME: BAR2 is not available if the device uses the CardBus function.
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*/
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addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel);
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@ -117,7 +115,6 @@ int nicintel_init(void)
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error_out_unmap:
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physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE);
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error_out:
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pci_cleanup(pacc);
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return 1;
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}
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@ -160,7 +160,6 @@ static int nicintel_spi_shutdown(void *data)
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pci_mmio_writel(tmp, nicintel_spibar + EECD);
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physunmap(nicintel_spibar, MEMMAP_SIZE);
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pci_cleanup(pacc);
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return 0;
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}
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@ -172,6 +171,7 @@ int nicintel_spi_init(void)
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if (rget_io_perms())
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return 1;
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/* No need to check for errors, pcidev_init() will not return in case of errors. */
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io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi);
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nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash",
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@ -54,7 +54,6 @@ static const struct par_programmer par_programmer_nicrealtek = {
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static int nicrealtek_shutdown(void *data)
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{
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/* FIXME: We forgot to disable software access again. */
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pci_cleanup(pacc);
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return 0;
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}
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@ -63,8 +62,8 @@ int nicrealtek_init(void)
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if (rget_io_perms())
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return 1;
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/* No need to check for errors, pcidev_init() will not return in case of errors. */
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io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek);
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if (register_shutdown(nicrealtek_shutdown, NULL))
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return 1;
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@ -100,8 +100,6 @@ static const struct bitbang_spi_master bitbang_spi_master_ogp = {
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static int ogp_spi_shutdown(void *data)
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{
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physunmap(ogp_spibar, 4096);
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pci_cleanup(pacc);
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return 0;
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}
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37
pcidev.c
37
pcidev.c
@ -154,6 +154,33 @@ uintptr_t pcidev_readbar(struct pci_dev *dev, int bar)
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return (uintptr_t)addr;
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}
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static int pcidev_shutdown(void *data)
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{
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pcidev_dev = NULL;
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if (pacc == NULL) {
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msg_perr("%s: Tried to cleanup an invalid PCI context!\n"
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"Please report a bug at flashrom@flashrom.org\n", __func__);
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return 1;
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}
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pci_cleanup(pacc);
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return 0;
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}
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int pci_init_common(void)
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{
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if (pacc != NULL) {
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msg_perr("%s: Tried to allocate a new PCI context, but there is still an old one!\n"
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"Please report a bug at flashrom@flashrom.org\n", __func__);
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return 1;
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}
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pacc = pci_alloc(); /* Get the pci_access structure */
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pci_init(pacc); /* Initialize the PCI library */
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if (register_shutdown(pcidev_shutdown, NULL))
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return 1;
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pci_scan_bus(pacc); /* We want to get the list of devices */
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return 0;
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}
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uintptr_t pcidev_init(int bar, const struct dev_entry *devs)
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{
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struct pci_dev *dev;
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@ -164,9 +191,8 @@ uintptr_t pcidev_init(int bar, const struct dev_entry *devs)
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int i;
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uintptr_t addr = 0, curaddr = 0;
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pacc = pci_alloc(); /* Get the pci_access structure */
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pci_init(pacc); /* Initialize the PCI library */
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pci_scan_bus(pacc); /* We want to get the list of devices */
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if(pci_init_common() != 0)
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return 1;
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pci_filter_init(pacc, &filter);
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/* Filter by bb:dd.f (if supplied by the user). */
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@ -244,6 +270,11 @@ struct undo_pci_write_data {
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int undo_pci_write(void *p)
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{
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struct undo_pci_write_data *data = p;
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if (pacc == NULL) {
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msg_perr("%s: Tried to undo PCI writes without a valid PCI context!\n"
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"Please report a bug at flashrom@flashrom.org\n", __func__);
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return 1;
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}
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msg_pdbg("Restoring PCI config space for %02x:%02x:%01x reg 0x%02x\n",
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data->dev.bus, data->dev.dev, data->dev.func, data->reg);
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switch (data->type) {
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@ -238,6 +238,7 @@ void internal_delay(int usecs);
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extern uint32_t io_base_addr;
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extern struct pci_access *pacc;
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extern struct pci_dev *pcidev_dev;
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int pci_init_common(void);
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uintptr_t pcidev_readbar(struct pci_dev *dev, int bar);
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uintptr_t pcidev_init(int bar, const struct dev_entry *devs);
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/* rpci_write_* are reversible writes. The original PCI config space register
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7
satamv.c
7
satamv.c
@ -60,7 +60,6 @@ static const struct par_programmer par_programmer_satamv = {
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static int satamv_shutdown(void *data)
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{
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physunmap(mv_bar, 0x20000);
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pci_cleanup(pacc);
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return 0;
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}
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@ -96,7 +95,7 @@ int satamv_init(void)
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mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000);
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if (mv_bar == ERROR_PTR)
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goto error_out;
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return 1;
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if (register_shutdown(satamv_shutdown, NULL))
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return 1;
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@ -159,10 +158,6 @@ int satamv_init(void)
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register_par_programmer(&par_programmer_satamv, BUS_PARALLEL);
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return 0;
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error_out:
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pci_cleanup(pacc);
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return 1;
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}
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/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
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