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mirror of https://review.coreboot.org/flashrom.git synced 2025-08-15 11:30:18 +02:00

flashchips: Add P25D80H

Adds support for the PUYA P25D80H flashchip.
Tested:     Probing RDID, reading, erasing, and writing to a single chip.
Programmer: A serprog implementation that was flashed to a Raspbery Pi Pico 2.
Parameters: Tested at 1Mhz
OS:         Raspberry Pi OS 64-bit running kernel version 6.12.38
Datasheet:  https://lcsc.com/datasheet/lcsc_datasheet_2304140030_PUYA-P25D80H-SSH-IT_C559199.pdf

Change-Id: I48612c369b555fb8c3f3cfe3ce0d00d3fd35a64f
Signed-off-by: James Vogenthaler <james.vogenthaler@mantech.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This commit is contained in:
James Vogenthaler
2025-07-24 16:34:14 -06:00
committed by Anastasia Klimchuk
parent 2beb555a6a
commit ff7091e9f4
2 changed files with 44 additions and 0 deletions

View File

@@ -146,3 +146,46 @@
.read = SPI_CHIP_READ,
.voltage = {2300, 3600},
},
{
.vendor = "PUYA",
.name = "P25D80H",
.bustype = BUS_SPI,
.manufacture_id = PUYA_ID,
.model_id = PUYA_P25D80H,
.total_size = 1024,
.page_size = 256,
/* supports SFDP */
/* OTP: 3 x 512 bytes */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_SCUR | FEATURE_CFGR,
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
.eraseblocks = { {256, 4096} },
.block_erase = SPI_BLOCK_ERASE_81,
}, {
.eraseblocks = { {4 * 1024, 256} },
.block_erase = SPI_BLOCK_ERASE_20,
}, {
.eraseblocks = { {32 * 1024, 32} },
.block_erase = SPI_BLOCK_ERASE_52,
}, {
.eraseblocks = { {64 * 1024, 16} },
.block_erase = SPI_BLOCK_ERASE_D8,
}, {
.eraseblocks = { {1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_60,
}, {
.eraseblocks = { {1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_C7,
}
},
.printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
.unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD,
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ,
.voltage = {2300, 3600},
},

View File

@@ -662,6 +662,7 @@
#define PUYA_P25Q06H 0x4010
#define PUYA_P25Q11H 0x4011
#define PUYA_P25Q21H 0x4012
#define PUYA_P25D80H 0x6014
/*
* The Sanyo chip found so far uses SPI, first byte is manufacturer code,