All CPPFLAGS and LDFLAGS for dependencies are handled by pkg-config
Change-Id: Ib7c11a0c8a7918562256480c4be0c95355f981c5
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In the Flash Component description register (FLCOMP) bit 30 reports the
capability of using dual output for fast read operation on the flash
component. According to various SPI Programming Guides (checked for
Panther Point, Lewisburg C620, Apollo Lake and Elkhart Lake) the dual
output is enabled when this bit is set and disabled if not. Currently the
logic displays it the other way around when parsing the descriptor.
This patch changes this so now if bit 30 in FLCOMP is not set, dual read
support for fast read operation is shown as disabled.
Change-Id: If6282ac8326ab0b92e9c70c09dba0299bf0deb6f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The pkg-config include path resolves the pciutils directory. So the
include is only the pci.h file.
Change-Id: I69dc8184d1d012fb695770cbf6f7c64e5a024453
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The --static flag of pkg-config returns also the LDFLAGS which are
required to link the library static. Use this flag to successfully
link against static libraries when the shared variant is not available.
This is the case in OpenBSD with libpci.
Change-Id: I6029a096c1ceca625789d18c88119d912d79bc0e
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some systems, e.g. OpenBSD, have clock_gettime / librt build into the
libc and therefore fail to link against it with -lrt. Thus, detect this
and link only if needed.
Change-Id: I2c1668a350aa0806fccfb4e9cd8b04861f085ee9
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The following describes the two mechanisms of testing done for
flash chip operations.
BUG=b:181803212
TEST=ninja test
Change-Id: Ie498ec55cce8460fc0b2e1fe27254d3a9f763fac
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This patch adds a macro MOCK_CHIP_CONTENT which represents a memory
state of a mock chip. The macro is used to initialise mock chip
memory at the beginning of a test (in setup_chip function).
Previously mock chip memory was not reset between tests. For
existing tests that did not matter, however new test for verify
operation (added later in this chain) needs mock chip memory to
be setup in a predictable way.
BUG=b:181803212
TEST=ninja test
Change-Id: I0d7623a601c207bfc62d54ab89d94cda56d85871
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
We've seen somewhat obscure test failures where the real fprintf()
function was passed a fake file returned by the fopen() mock.
Although the code that caused the specific failure was cros-specific,
adding an fprintf() mock should help avoid future debugging.
TEST=ninja test
BRANCH=none
BUG=b:217661133
Change-Id: I3f8594ea24d17436a7932732d9d05416b804dc93
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61708
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Elkhart Lake has a chipset called Mule Creek Canyon which is quite
compatible with 300 series chipsets. There are a few differences though,
e.g. different encoding for the SPI clock values for read and write in
the FLCOMP register. In addition Elkhart Lake has a new PCI device ID
for the SPI controller which is added, too.
TEST=Read and flash complete flash on Siemens MC EHL1
Change-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Calling libflashrom entry-points that internally dispatch to
fmap_lsearch() can result in a integer overflow. Therefore
validate the length paramter before attempting to use it.
BUG=none
TEST=`make`
Change-Id: Ifb408c55c3b69ddff453dcc704b7389298050473
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Spotted-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61545
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:204488958
TEST=Check that the following scenarios still behave properly:
1) probe-read-verify-erase section-write-reboot
on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E
2) flashrom binary built before and after this patch with command
`make clean && make CONFIG_EVERYTHING=yes VERSION=none`
is the same
Change-Id: I7ca2902b7caaa95418b828b068c661afafdcd171
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Initialisation of swseq_data and hwseq_data gets its own function,
which is called from init_ich_default. This makes init_ich_default
more readable.
This patch also gives a name to (previously anonymous) struct
swseq_data. Its sibling struct hwseq_data already has a name. Structs
need names to be able to declare function parameters.
BUG=b:204488958
TEST=Check that the following scenarios still behave properly:
1) probe-read-verify-erase section-write-reboot
on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E
2) probe and read on Panther Point (7 series PCH)
Change-Id: I7d62b1b380e497b82dcae1284d752204cc541bd3
Tested-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Extract processing of ich_spi_mode into a separate function which
is called from init_ich_default. This makes init_ich_default more
readable and avoids one local variable.
BUG=b:204488958
TEST=Check that the following scenarios still behave properly:
1) probe-read-verify-erase section-write-reboot
on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E
2) probe and read on Panther Point (7 series PCH)
Change-Id: I20e2379a6fd58c9346f0a2d6daf2b8decf1f6976
Tested-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
ich_init_spi is very long, but logically it can be split. Init
function detects the chipset and then the rest of operations depends
on the chipset.
Init function is more readable now, it consists of only a switch.
Initialisation of hwseq and swseq that used to happen in the
beginning of init function now moved to init_ich_default, because
hwseq and swseq are only used for chipsets served by init_ich_default.
BUG=b:204488958
TEST=Check that the following scenarios still behave properly:
1) probe-read-verify-erase section-write-reboot
on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E
2) probe and read on Panther Point (7 series PCH)
3) on machine with ich7 chipset, output from probe and read is
the same between master and this patch
Change-Id: I6789bc456a4878e6555831ae0b80ecbdbf62938b
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: Nico Huber <nico.h@gmx.de>
Tested-by: Nicholas Chin <nic.c3.14@gmail.com>
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58735
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a spi_master interface supporting MediaTek MST9U ISP mode.
Autodetect the bus type via I2C_FUNC_I2C, and use the appropriate
read/write commands, in case the MST9U is attached to smbus.
TEST=Successfully programmed SPI on test hardware.
Change-Id: I24adb14e7b4f7160e1c3ff941774064d5a81e820
Signed-off-by: Neill Corlett <corlett@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
These helpers are only used by the CLI logic and so we localise
them here to move towards cli_classic being a pure libflashrom
user.
BUG=b:208132085
TEST=`make`
Change-Id: If1112155e2421e0178fd73f847cbb80868387433
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This allows for moving all the do_*() helper functions
use for the cli from flashrom.c within static local functions
in cli_classic.c
BUG=b:208132085
TEST=`make`
Change-Id: Ia0abec655a682ca449d0e8ba620886a2d616b86d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
The JEDEC SFDP specification JESD216A (1.5) adds five new DWORDs to the
Basic Flash Parameter Table. Later versions of the spec add even more
fields. This increases the table being read from 36 bytes to currently
64 bytes and makes flashrom bail out for any SFDP version >= 1.5 due to
a static table length check.
This was discovered on a GigaDevice GD25B127DSIGR from 2021 with SFDP
revision 1.6, while another flash of the same model from 2020 with SFDP
revision 1.0 was detected fine by flashrom.
GD25B127DSIGR - 2020 version:
Probing for Unknown SFDP-capable chip, 0 kB: SFDP revision = 1.0
SFDP number of parameter headers is 2 (NPH = 1).
SFDP parameter table header 0/1:
ID 0x00, version 1.0
Length 36 B, Parameter Table Pointer 0x000030
GD25B127DSIGR - 2021 version:
Probing for Unknown SFDP-capable chip, 0 kB: SFDP revision = 1.6
SFDP number of parameter headers is 2 (NPH = 1).
SFDP parameter table header 0/1:
ID 0x00, version 1.6
Length 64 B, Parameter Table Pointer 0x000030
...
Length of the mandatory JEDEC SFDP parameter table is wrong (64 B),
skipping it.
The specification says that changes of the minor SFDP revision will
maintain compatibility. Thus, simply check for the minimal required
table length, which is 16 bytes for legacy Intel pre-SFDP and 36 bytes
for SFDP.
Change-Id: Id84cde4ebc805d68e2984e8041fbc48d7ceebe34
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The Makefile recently gained finer-grained programmer dependency lists
allowing it to track which enabled programmers assume various things
about the system, like availability of libraries or the CPU
architecture. This change implements the same changes in the Meson
configuration file.
This fixes a number of programmers to correctly build on non-x86
systems, because they were previously misclassified as dependent on x86
architectural features but actually only used PCI.
BUG=none
TEST=meson build succeeds on both x86 and ARM
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Iae93111fd48865f3fe8dd0eb637349b9a0c4affc
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
The changes to hwaccess in commit 49d758698a0dd166679c48b1a2785e50e9b0cc83
cause build failure on non-x86 systems because the hwaccess_x86_*
headers are included in some files that are built for all platforms
(particularly those in the internal programmer) and those headers in
turn include <sys/io.h> which only exists on x86.
This change avoids including those headers on non-x86 platforms so
the internal programmer can be built without errors.
The comment on the stub implementation of rget_io_perms() is also
modified to remove references to non-x86 platforms, since that file is
only built on x86 now.
BUG=None
TEST=meson build succeeds for both x86 and ARM targets
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61194
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Aspire towards a goal of making cli_classic more of just
a user of libflashrom than having quasi-parallel paths in
flashrom.c
This converts the do_read() provider wrapper into a pure
libflashrom user.
BUG=b:208132085
TEST=`$ sudo ./flashrom -p internal -r /tmp/bios.bin`
TEST=`$ sudo ./flashrom -p internal -l /tmp/layout -i FOO -r /tmp/foo.bin`
Change-Id: Id2addadb891c482ee3f69da806062d7a88776675
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Inline emergency_help_message() to cli_classic call site.
This leaves do_erase() a redudant wrapper and moves us a step
closer to cli_classic as a pure libflashrom user by using
flashrom_flash_erase().
BUG=b:208132085
TEST=`flashrom -E`
Change-Id: I8566164e7dbad69cf478b24208014f10fb99e4d0
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This change fixes a bug on handling the extract operation. The extract
operation reads out the layout regions to filenames corresponding to the
respective layout region names. read_flash_to_file() does this work via
write_buf_to_include_args(). This change makes the call to
write_buf_to_file() optional as it is still required for -r (read
operation) but not for -x (extract operation).
BUG=b:209512852
TEST=flashrom -x
Fixes: commit ce983bccaab450d358854494f15c2d8a1846d56b
Change-Id: Ibc9a4e2966385863345f06662521d6d0e4685121
Signed-off-by: Daniel Campello <campello@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
These targets are all called together. No need to have them individual.
Change-Id: Ic76f923bca2beb6f95b8ea0cced4569b07e9b9ba
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use the order in which the targets get executed.
Change-Id: Ic45c2fc98c679ac7be4ee2860d72b517b8b67a17
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use `make HAS_LIBPCI=yes/no` to override the pkg-config detection and
`CONFIG_LIBPCI_CFLAGS` and `CONFIG_LIBPCI_LDFLAGS` to set cflags and
ldflags manually. The optional dependency of libpci libz, is
automatically handled by pkg-config.
Change-Id: I21b4a261b34b7e688635fc6e20b7beebfa64c7ed
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Let programmer only depend on the kind of hardware access method they
really need. Libpci no longer depends on all hardware access types since
each programmer handles this individually.
Change-Id: I5bdafaa3c5023ad6c4a695493eeddf11bc148085
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The mmio_le/be_read/writex functions are used for raw memory access.
Bundle them with the physmap functions.
Change-Id: I313062b078e89630c703038866ac93c651f0f49a
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As a part of effort to convert command line (and everything else)
to be libflashrom users, chip tests need to be converted as well.
TEST=ninja test
Change-Id: I965598cfa74e3fb7d0780ad34491f4057617691e
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
As a part of effort to convert command line (and everything else)
to be libflashrom users, chip tests need to be converted as well.
TEST=ninja test
Change-Id: I4493d4f269595783830c39a720b0a8963eab9daa
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
As a part of effort to convert command line (and everything else)
to be libflashrom users, chip tests need to be converted as well.
TEST=ninja test
Change-Id: I38529a6b4d79882f50068b3628089b178dbe0a50
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
dediprog_bulk_read_poll()'s finish argument allows it to be used in two
distinct cases: where dediprog_bulk_read_poll will be called as part of
a loop (finish=0) and where dediprog_bulk_read_poll should wait for all
outstanding transfers to finish (finish=1). In both cases,
dediprog_bulk_read_poll() calls libusb to process events with a 10
second timeout.
After dediprog_spi_bulk_read() has queued the last transfers, it calls
dediprog_bulk_read_poll() with finish=0 when it should be finish=1.
finish=0 just happens to work because frequently the transfers finish in
the 10 second timeout.
Signed-off-by: Rick Altherr <rick@oxidecomputer.com>
Change-Id: If7cb541742c8620358c8e04275d8316131b2d1ab
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Make the linux_mtd driver treat any negative return value from the
MEMERASE ioctl as an error. Previously it only treated -1 as an error.
BUG=b:213561594,b:210973586,b:182223106
BRANCH=none
TEST=builds
Change-Id: I40cfbdee2ab608fbe6c17d9cac6ec53ff224d9a4
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
While using the libflashrom API to read specific regions
there is no currently no general way to find the offset
into the read buffer of the expected region.
flashrom_layout_include_region() probably should have
returned the region offset and size if it was included.
However to avoid a change in API signature we can instead
hoist up get_region_range() into the API to be called after.
BUG=b:207808292
TEST=`make` && tested in porting cbfstool use-case.
Change-Id: I8cf95b5eaec943a51d0ea668f26a56bf6d6b4446
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
The it8212 programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: Iab859fb6be6cab094c9c6ce4b3e8eac0e5ff84ab
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60869
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The satasii programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: I54d65561ff024d3c181d11c6518a4612c2ab0399
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60848
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ogp_spi programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: I1f3f34e33f77159fa0cdea150e1f408ce9d943f0
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The nicintel_spi programmer does not use x86 IO Ports. Remove the
dependency to it.
Change-Id: I3e7451eceb1f01de21da934c9559dbf2f06e7e54
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60846
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The nicintel_eeprom programmer does not use x86 IO Ports. Remove the
dependency to it.
Change-Id: I5fd42572fd29f5d7fd749c2836eac3e68c947946
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60845
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The nicintel programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: Ibe609ff8f8fdbdf2a7de8e1922325ca4ad56a9e7
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60844
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The gfxnvidia programmer does not use x86 IO Ports. Remove the
dependency to it.
Change-Id: I1f0341390ccb698bc435760f4ead7de54e429a6e
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60843
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The drkaiser programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: I86bad947298a1166ff1e768f7d0b75a90e574696
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60842
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The atavia programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: I1fa866b3b07adf5f7a51d58f53d6cad1f88d7210
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60841
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
