The parallel internal programmer is its own implementation. Move
it and call into it from the top-level internal.c programmer
implementation.
Change-Id: Idabeceb59a36680f5fbb45d3ee4bd5dbf837373b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/71834
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1) Add function to flatten out the addresses of the flash chip as per
the different erase functions. This function will return a list of
layouts which is dynamically allocated. So after use all the layouts as
well as the list itself should be freed. The free_erase_layout function
does that.
2) Add function to align start and end address of the region (in struct
walk_info) to some erase sector boundaries and modify the region start
and end addresses to match nearest erase sector boundaries. This
function will be used in the new algorithm for erase function selection.
3) Add function that returns a list of sectors (as seen by the first
erase function) that need erasing.
4) Add a function to call the erase algorithm.
Change-Id: Ic57ca1cca3d1646543f6b5939ba9c35db8d08256
Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/65844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
While super i/o is related to the internal programmer it
isn't actually _the_ internal programmer. Move register
logic to its own object consistent with other programmer
types.
Change-Id: I9a4c3e12bce5d22492c8d1b8f4a3f49d736dcf31
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/71577
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a bash script for the flashrom CLI that auto-completes the command
sequence. The script is generated from a template by substituting a
list of enabled programmers. It requires an extra `bash-completion`
package to work, but, fortunately, it's installed on most systems.
Build system changes:
meson:
provide option `bash_completion` to determine if the script should
be installed (depends on option `classic_cli`).
makefile:
make a list of enabled programmers (by using CONFIG_* variables)
to do substitution manually
Change-Id: Ie68bc91c3cea4de2ffdbeffd07e48edd8d5590e1
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
These specific git hooks are only needed when someone wants to push a
patch to upstream and so it's not needed to run it in every make call.
Beside that, we also don't know the environment in which this is
executed and it might not be wanted.
Thus, add a new make target `gitconfig` and move the install command to
it. It can be used by running `make gitconfig`.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Ib83568c7ff149a8ec34ad7e92720c36a89def7bd
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Add a new programmer driver for the DirtyJTAG project (a USB-JTAG
firmware for STM32 MCUs).
Successfully tested with DirtyJTAG 1.4 running on an Olimex STM32-H103
development board and a SST25VF020B SPI flash chip.
Change-Id: Ic43e9a014ed7d04e429e73b30c9dcfdde1a78913
Signed-off-by: Jean THOMAS <virgule@jeanthomas.me>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67878
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This free's up namespace pollution and a layer of ifdef.
BUG=b:242246291
TEST=builds
Change-Id: Id098343b9b79fd9b01c7dc48e64756ad350f9d83
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
This is analogous to spi.c and opaque.c however parallel
logic was previously never consoldiated.
This free's up flashrom.c from namespace pollution.
BUG=b:242246291
TEST=builds with both make and meson.
Change-Id: Ie08e2e6c51ccef5281386bf7e3df439b91573974
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Constructing a buffer from a read file is auxiliary
functionality to the core flashrom algorithms. Move
aside to decrease the overall complexity of flashrom.c
BUG=b:242246291
TEST=builds
Change-Id: Ia6e1eeb876722899defb5b75346d1f22c70bfbd1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Benn <evanbenn@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
When a library is found, then print its version in the config target.
Change-Id: Ie1ff8107311247fba9e5caa252d559447c871867
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Mark programmers requiring RAW_MEM_ACCESS, X86_IO_PORT and X86_MSR as
unsupported on Windows
TEST=Buils on Cygwin (Windows 11, amd64, gcc 11.3.0)
Change-Id: If70691a9eae40c394a06d11349bedefa40586f4a
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66546
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Flashrom does no longer rebuild everything if `make` is executed.
Now the rule config will run, if needed, before any ‘.o’ is built,
but no ‘.o’ will be built because there is no config file.
https://www.gnu.org/software/make/manual/make.html#Prerequisite-Types
Change-Id: Ie9225b79c0eb27cb041654d703cde5efc769cbf2
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Commit df0bbf0 renamed the programmer lspcon_i2c_spi to parade_lspcon
but also introduced a typo in its Makefile config option. Fix that.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Ie9193931a4483bba129da513554ce7ca0b790374
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Thomas Heijligen <src@posteo.de>
The chip targeted by the `lspcon_i2c_spi` programmer is a Parade PS175.
Rename the programmer to match the chips vendor / family instead of the
generic LSPCON protocol. Remove the `_i2c_spi` ending in preparation to
become an opaque master. The chip is visible on an Acer Chromebox CXI4.
https://www.paradetech.com/products/ps175/https://www.acer.com/ac/en/US/content/series/acerchromeboxcxi4
TEST: `make CONFIG_PARADE_LSPCON=yes` and
`meson build -Dconfig_parade_lspcon=true` produces flashrom
binaries with the parade_lspcon programmer included.
Change-Id: I9148be6d9162c1722ff739929ca5e181b628dd57
Signed-off-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/65547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This code was originally introduced by ITE for now exceedingly old
Chromebooks. The code has had very little attention to maintain it,
unlikely tested for a long time and now seems to be just a technical
burden to the flashrom project.
If someone is later interested it could be resurrected for reference
from git history. However, it needs quite a bit of work to bring it back
into maintainable order.
BUG=b:156143896,b:170689483
TEST=tree builds under meson+make and unit tests pass.
Change-Id: I5e8cafd73db837941c518f0e2d72d8192274fd79
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/65378
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Just a trivial patch to fix a few errors found by codespell.
Here's the command I used:
codespell -S subprojects,out \
-L fwe,dout,tast,crate,parms,claus,nt,nd,te,truns,trun
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62840
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move all header files to the new `include` directory.
Adapt include directives and build systems to the new directory.
Change-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
STANDALONE mode was used to build flashrom without having support for
file handling. This was relevant to build libflashrom on top of
libpayload. For a while now, the code which is covered by STANDALONE has
moved to cli_*.c and is not used for libflashrom. Therefore we can drop
STANDALONE mode.
Change-Id: I58fb82270a9884a323d9850176708d230fdc5165
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The NEED_PCI macro is only used to guard prototypes. This is not needed.
Change-Id: I6895b795bc96b3e251700bff4b0054407aac789a
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add functions like
`uint32_t read_le32(const void *base, size_t offset);`
Read a 32 bit unsigned from a base with an offset.
Having prototypes and a macro generated implementation makes it easier
to read, understand and spot errors in one of them.
Change-Id: Idde177acf8bc5f94cd046b6539dc31532c98e452
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/31016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Starting to move the platform dependent code to platform/ and provide
the abstraction through the platform.h header.
Change-Id: I35640282d451960f2a329ae24339ec05dbae6d30
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Split the code for endian conversion into separate files for big and
little endian. The buildsystem selects the correct file for the used
endianness. Replace the swab macros with `static inline` c functions.
Define macros for returning the same or swapped value. Call those macros
in the endian specific files.
Change-Id: I86d38d816b37c283279c485fac8027f8fb94364a
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Align the usage of serial function with the selection of other
dependencies.
Change-Id: Ica951e76d6362b01f09d23a729a2a6049e7f0b66
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Allow chips to specify functions that map status register bits to
protection ranges. These are used to enumerate available ranges and
determine the protection state of chips. The patch also adds a range
decoding function for the example chips. Many other chips can also be
handled by it, though some will require different functions (e.g.
MX25L6406 and related chips).
Another approach that has been tried in cros flashrom is maintaining
tables of range data, but it quickly becomes error prone and hard to
validate.
Using a function to interpret the ranges allows compact encoding with
most chips and is flexible enough to allow chips with less predictable
ranges to be handled as well.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=dumped range tables, checked against datasheets
Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Use a conditional function for the statement. This limits the decision
to one line instead of multiple places.
Change-Id: Iee66dbc609bd5c6eb9d04b457f4508911b2e6560
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The internal programmer has platform independent code for x86 and linux
based code for mipsel. Furthermore the internal programmer can call the
linux mtd programmer when available.
Enable the internal programmer on x86 or linux.
Change-Id: Ia607ea60c3d7d15fe231fa412595992dadc535ad
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
All CPPFLAGS and LDFLAGS for dependencies are handled by pkg-config
Change-Id: Ib7c11a0c8a7918562256480c4be0c95355f981c5
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The --static flag of pkg-config returns also the LDFLAGS which are
required to link the library static. Use this flag to successfully
link against static libraries when the shared variant is not available.
This is the case in OpenBSD with libpci.
Change-Id: I6029a096c1ceca625789d18c88119d912d79bc0e
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some systems, e.g. OpenBSD, have clock_gettime / librt build into the
libc and therefore fail to link against it with -lrt. Thus, detect this
and link only if needed.
Change-Id: I2c1668a350aa0806fccfb4e9cd8b04861f085ee9
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a spi_master interface supporting MediaTek MST9U ISP mode.
Autodetect the bus type via I2C_FUNC_I2C, and use the appropriate
read/write commands, in case the MST9U is attached to smbus.
TEST=Successfully programmed SPI on test hardware.
Change-Id: I24adb14e7b4f7160e1c3ff941774064d5a81e820
Signed-off-by: Neill Corlett <corlett@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
These targets are all called together. No need to have them individual.
Change-Id: Ic76f923bca2beb6f95b8ea0cced4569b07e9b9ba
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use the order in which the targets get executed.
Change-Id: Ic45c2fc98c679ac7be4ee2860d72b517b8b67a17
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use `make HAS_LIBPCI=yes/no` to override the pkg-config detection and
`CONFIG_LIBPCI_CFLAGS` and `CONFIG_LIBPCI_LDFLAGS` to set cflags and
ldflags manually. The optional dependency of libpci libz, is
automatically handled by pkg-config.
Change-Id: I21b4a261b34b7e688635fc6e20b7beebfa64c7ed
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Let programmer only depend on the kind of hardware access method they
really need. Libpci no longer depends on all hardware access types since
each programmer handles this individually.
Change-Id: I5bdafaa3c5023ad6c4a695493eeddf11bc148085
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The mmio_le/be_read/writex functions are used for raw memory access.
Bundle them with the physmap functions.
Change-Id: I313062b078e89630c703038866ac93c651f0f49a
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The satasii programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: I54d65561ff024d3c181d11c6518a4612c2ab0399
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60848
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ogp_spi programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: I1f3f34e33f77159fa0cdea150e1f408ce9d943f0
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The nicintel_spi programmer does not use x86 IO Ports. Remove the
dependency to it.
Change-Id: I3e7451eceb1f01de21da934c9559dbf2f06e7e54
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60846
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
