Straight from the data sheet, not tested.
Corresponding to flashrom svn r175 and coreboot v2 svn r3036.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Corresponding to flashrom svn r174 and coreboot v2 svn r3033.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Corresponding to flashrom svn r173 and coreboot v2 svn r3032.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Improve model number printing.
Add EN29F002(A)(N)B support while I'm at it.
Corresponding to flashrom svn r172 and coreboot v2 svn r3031.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Markus Boas <bios@ryven.de>
The continuation ID code does not go further than checking for IDs of
the type 0x7fXX, but does this for vendor and product ID. The current
published JEDEC spec has a list where the largest vendor ID is 7 bytes
long, but all leading bytes are 0x7f. The list will grow in the future,
and using a 64bit variable will not be enough anymore.
Besides that, it seems that the location of the ID byte after the first
continuation ID byte is very vendor specific, so we may have to revisit
that code some time in the future.
(Suggestion for a new encoding:
Use a two-byte data type for the ID, the lower byte contains the only
non-0x7f byte, the upper byte contains the number of 0x7f bytes used as
prefix, which is the bank number minus 1 the vendor ID appears in.)
Add support for EON EN29F002AT.
Corresponding to flashrom svn r171 and coreboot v2 svn r3030.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
This fixes a few vendor IDs to conform with JEDEC publication 106W
(JEP106W), adds some device IDs and provides information about
non-conforming IDs. The EON change is left to the patch adding EON
chips.
This patch should have no effect on code generation.
Corresponding to flashrom svn r170 and coreboot v2 svn r3029.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Fix that. Page size is uniform 256 bytes for SPI.
A sector/block size field in struct flashchip would be nice, though.
Corresponding to flashrom svn r169 and coreboot v2 svn r3027.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Pretty-print the chip status register (including block lock information)
for ST M25P family and Macronix MX25L family chips.
Corresponding to flashrom svn r168 and coreboot v2 svn r3026.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Untested, but verified against the data sheet.
Corresponding to flashrom svn r167 and coreboot v2 svn r3025.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Add support for ST M25P05-A, M25P10-A, M25P20, M25P40, M25P16, M25P32,
M25P64, M25P128.
ST M25P80 support is already there. Not tested, but conforming to data
sheets and double checked.
Corresponding to flashrom svn r166 and coreboot v2 svn r3012.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
To make it easier to add new SPI chips to flashchips.c, rename functions
with multiple possible opcodes from linear numbering at the end (_1, _2)
to include the opcode at the end (_60, _c7).
That way, you only have to take a short look at the data sheet and
choose the right function by appending the opcode listed in the data
sheet. No functional changes.
Corresponding to flashrom svn r165 and coreboot v2 svn r3009.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>
Detection was tested. Print status register before erase to help
debugging block locks.
Corresponding to flashrom svn r164 and coreboot v2 svn r3008.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per
http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html
Corresponding to flashrom svn r162 and coreboot v2 svn r2997.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Corresponding to flashrom svn r161 and coreboot v2 svn r2995.
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Attached is a patch that enables AMD Geode CS5536 chipset support. I
have tested it successfully on a MSM800 board from digital logic.
Corresponding to flashrom svn r160 and coreboot v2 svn r2967.
Signed-off-by: Lane Brooks <lbrooks@mit.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
The JEDEC probe routine had a delay of 10 us after entering ID mode
and this was insufficient for the 29C020. The data sheet claims we
have to wait 10 ms, but tests have shown that 20 us suffice. Allow for
variations in chip delays with a factor of 2 safety margin.
Corresponding to flashrom svn r159 and coreboot v2 svn r2962.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
Detection and reading works, writing is not tested.
Corresponding to flashrom svn r158 and coreboot v2 svn r2903.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Looking through the sources of Uniflash utility I found that this chip
is no more no less than low-voltage variant of Am29F040B but with
different ID.
So I created a very quick patch (attached).
Corresponding to flashrom svn r157 and coreboot v2 svn r2897.
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
This has been tested by Harald Gutmann <harald.gutmann@gmx.net> with a
MX25L4005 chip.
Corresponding to flashrom svn r154 and coreboot v2 svn r2876.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Corresponding to flashrom svn r153 and coreboot v2 svn r2875.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
The first chip the code was tested and verified with is the Macronix
MX25L4005, but other chips should work as well. Timeouts are still
hardcoded to data sheet maxima, but the status register checking code is
already there. Thanks to Harald Gutmann for the initial code on which
this is loosely based.
Corresponding to flashrom svn r152 and coreboot v2 svn r2874.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Corresponding to flashrom svn r151 and coreboot v2 svn r2873.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
This has been confirmed by Ed Swierk in
http://www.mail-archive.com/linuxbios@linuxbios.org/msg09788.html .
Corresponding to flashrom svn r150 and coreboot v2 svn r2868.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
- Install binary in /usr/sbin (not /usr/bin), as it's a root-only tool.
- Rename manpage from flashrom.1 to flashrom.8, as section 8 contains
"System administration commands (usually only for root)".
- Actually install the manpage upon 'make install'.
Corresponding to flashrom svn r149 and coreboot v2 svn r2866.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Corresponding to flashrom svn r148 and coreboot v2 svn r2864.
Signed-off-by: Michael van der Kolff <mvanderkolff@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The SPI chip finding and SPI chip accessor code is moved as well. This
can be split later if we feel like it.
The non-use of svn cp is intentional because the only history we'd
have to preserve are a few commits which were early prototypes of chip
identification code. For those who intend to look at that history, they
can look at board_enable.c revision 2853.
Corresponding to flashrom svn r145 and coreboot v2 svn r2857.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Also minor changes to remove tab-space combinations where possible.
Corresponding to flashrom svn r144 and coreboot v2 svn r2850.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Corresponding to flashrom svn r143 and coreboot v2 svn r2847.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Corresponding to flashrom svn r142 and coreboot v2 svn r2846.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
The help implied that writes happen by default, which they don't. Fix
the text, and say something when we dont specify any commands.
Corresponding to flashrom svn r141 and coreboot v2 svn r2820.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
It introduces a generic SPI host driver for the IT8716F Super I/O
which will enable easy SPI programming without having to care for the
peculiarities of the SPI host.
To activate probing for the IT8716F, you have to use the gigabyte:m57sli
mainboard override. SPI support will then use the gathered SPI host data
to access the SPI flash.
This has been tested sucessfully by Ward Vandewege <ward@gnu.org> on the
GA-M57SLI v2.0, which has a MX25L4005 SPI flash part.
Corresponding to flashrom svn r140 and coreboot v2 svn r2817.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>
Right now this is hardcoded to the Gigabyte M57SLI board. It works only
with rev 2.0 of the board, but it will bail out on earlier versions, so
no damage can occur.
Corresponding to flashrom svn r139 and coreboot v2 svn r2811.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>
Corresponding to flashrom svn r138 and coreboot v2 svn r2770.
Signed-off-by: Alex Beregszaszi <alex@rtfs.hu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Corresponding to flashrom svn r137 and coreboot v2 svn r2769.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Corresponding to flashrom svn r136 and coreboot v2 svn r2768.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
I'm self-ack'ing this, as the origin of the code in udelay.c (and thus
the license and copyright owner) is pretty clear.
The code which is now in udelay.c was split out from flash_rom.c in r1428,
and flash_rom.c, in turn, has been around since the beginning and had a
'Copyright 2000 Silicon Integrated System Corporation' line as well as the
usual GPLv2-or-later license header.
Corresponding to flashrom svn r135 and coreboot v2 svn r2767.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Add a copy of the GPL in the flashrom repository as it's an independent
project (being packaged by distros, among other things).
Corresponding to flashrom svn r134 and coreboot v2 svn r2764.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
No changes in content of the files.
Corresponding to flashrom svn r131 and coreboot v2 svn r2751.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Corresponding to flashrom svn r130 and coreboot v2 svn r2748.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Corresponding to flashrom svn r129 and coreboot v2 svn r2747.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Corresponding to flashrom svn r128 and coreboot v2 svn r2746.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Corresponding to flashrom svn r127 and coreboot v2 svn r2745.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
The first byte of the flash chip was read at the start of the function
and later written back to address 0 if the flash chip was not identified
as SST28SF040, which means most of the time. This write caused corruption
of flash contents when verifying a SST49LF160C part.
Corresponding to flashrom svn r126 and coreboot v2 svn r2744.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Peter Stuge <peter@stuge.se>
