This may seem too big just to support yet another flash chip, but in
reality it brings support for whole new family of S25FS
Spansion/Cypress flash chips. These chips require handling of some
special status registers for erasing or writing, with very specific
timing checks in place.
For example, WIP status bit will remain being set to 1 if erase or
programming errors occur, and in that case chip 'software reset' has
to be performed otherwise the chip will remain unresponsive to all
further commands. Also, special CR3NV register (Configuration Register
3 Nonvolatile) status bits needs to be read and set by using RDAR
(ReaD Any Register) and WRAR (WRite Any Register) OP commands, and
these states are needed to determine which type of reset feature is
enabled at the time (legacy or S25FS type) in the first place,
determine whether Uniform or Hybrid sector architecture is used
at the time, or set programming buffer address wrap point (256 or 512
bytes). Furthermore, S25FS chip status register has to be restored to
its original state (hence that ugly CHIP_RESTORE_CALLBACK) following
erasing or writing, failing to do so may result in host being unable
to access data on the chip at all.
Finally, although this brings support for the whole family of chips,
I only have one such chip to do the actual testing, S25FS128S (Small
Sectors), which I had fully tested on ch341a and FT4232H programmers,
with confirmed working probe, read, erase and write.
Full summary of changes are here:
flashchips:
add new flashchip sctructure property:
.reset
add chip definitions:
S25FS128S Large Sectors
S25FS128S Small Sectors
flash:
add macro (chip_restore_func_data call-back):
CHIP_RESTORE_CALLBACK
flashrom:
add struct:
chip_restore_func_data
add call-back function:
register_chip_restore
spi:
add OP codes:
CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST
add register bit function definitions:
CR3NV_ADDR, CR3NV_20H_NV
add timers:
T_W, T_RPH, T_SE
spi25:
refactor (based on chromiumos implementation) function:
spi_poll_wip
port these functions from chromiumos:
probe_spi_big_spansion
s25fs_software_reset
s25f_legacy_software_reset
s25fs_block_erase_d8
spi25_statusreg:
port these functions from chromiumos:
spi_restore_status
s25fs_read_cr
s25fs_write_cr
s25fs_restore_cr3nv
Most of the ported functions are originally from s25f.c found at
https://chromium.googlesource.com/chromiumos/third_party/flashrom
with exception of spi_restore_status which is defined in
spi25_statusreg.c. The rest of macros and OP codes are defined in
same files as in this commit.
Change-Id: If659290874a4b9db6e71256bdef382d31b288e72
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Clean up some confusion of implicit copies by indirection.
This allows the caller of register_spi_master() to have it's
internal state in the expected way.
Also add an error when the mpu reset fails on init.
BUG=b:148746232,b:153027771,b:140394053
BRANCH=none
TEST=builds
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I66ba4ffeb696309b8ad5b5ba58650630e8feefa9
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Commit 92d6a86 ("Refactor Intel Chipset Enables") eliminated a check
to disable SPI when ICH7 has booted from LPC, as the hardware does not
support it. Therefore, when flashrom probes the SPI bus, it times out
waiting for the hardware to react, for each and every SPI flash chip.
This results in very long delays and countless instances of the error:
Error: SCIP never cleared!
To prevent this, bring back part of the lost check. Probing for LPC and
FWH when booted from SPI does not seem to cause any problems on desktop
mainboards with ICH7, so don't disable LPC nor FWH if that is the case.
Tested on ECS 945G-M4 (ICH7, boots from LPC), works without errors.
Change-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
If the `--flash-contents` switch is specified more than once, it will
result in a memory leak. Therefore, allow this option only once.
Change-Id: I530933c9a6431580fe4645396bb363939472a80a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39972
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:153515968
BRANCH=kukui
TEST=flash coreboot on kakadu and get successful result.
Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967
Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40275
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: Edward O'Callaghan <quasisec@chromium.org>
This adds support for the Parade lspcon usb-c to HDMI protocol
translater part that is i2c-controlled. The support allows the
host to reach the SPI ROM that hangs off the part where it
stores its firmware.
Usage is as follows:
flashrom -p lspcon_i2c_spi:bus=X
where X is the bus number.
BUG=b:148746232
BRANCH=none
TEST=tested with following commands, read/write/erase works good.
flashrom -p lspcon_i2c_spi:bus=7 -r /tmp/foo;
flashrom -p lspcon_i2c_spi:bus=7 -E;
flashrom -p lspcon_i2c_spi:bus=7 -w /tmp/foo;
Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
See https://www.kernel.org/doc/Documentation/i2c/ for details.
This creates common interface for I2C access functions, and adds
implementation for linux I2C functions.
BUG=b:148746232
BRANCH=none
TEST=build success
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: Ie0487824dfb71970bede17f617dbbb30ddf78c12
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39686
Tested-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Turns out CONFIG_RAIDEN was missing in the LIBUSB1
as no overrides. Credit to HAOUAS Elyes for spotting this.
Change-Id: I7dd26665a0133175949c11717837e9de68a1bf71
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The raiden_debug programmer is of type USB. However, it does not set the
field `devs.dev`, which will result in a segfault when trying to print
the devices of the non-existing table.
Fix that by replacing `devs.note` with `devs.dev` and adding an empty
device table. Since Device IDs are not used to match programmers,
nothing could be added to the table.
TEST=Running `flashrom -L` no longer segfaults and returns normally.
Change-Id: Ie4171a11384c34abb102d1aadf86aa1b8829fc04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Support GD25WQ80E, which is the internal flash of IT81202.
TEST=Building flashrom and flashing FW image into IT81202 successfully.
Change-Id: Ib5feaa6ecc7b11b2218e5f02c087b4331388bef8
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
32Mbit (4MiB) [x1/x2/x4] Wide Voltage Range (VCC 1.65V-3.6V). It is
similar to the already-supported MX25R6435F, but the total size is
halved.
Tested on ch341a, FT4232H and FT2232H (PicoTAP) programmers, confirmed
working probe, read, erase and write.
Fixes: https://github.com/flashrom/flashrom/issues/43
Change-Id: I6e79115adba17d13d24bc85d78707d53fd4a0be5
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested reading, writing and erasing the internal flash chip using an
Acer Aspire ES1-572 laptop with an Intel i3-6006U. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall
follow suit as well.
Change-Id: Ib8ee9b5e811df74d2f48bd409806c72fe862bc24
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Add a delay following the AP and EC flash enable requests. This allows
any power rails enabled by these signals to settle and to meet the power
on to first SPI write timing requirements.
Forward ports the downstream commit:
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2036738
Change-Id: I4c1777777ee67580605c6e6f4c0c228cccc392c7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This overcomes a problem with the ServoMicro where USB packets can be
ack'd by the device without triggering interrupts or loading data into
the USB endpoints. The retry mechanism attempts the USB read 3 times
before reattempting the write call to avoid performing multiple SPI
transfers due to a USB problem. This process repeats 3 times before we
return the last error code. Intermediary problems are reported in the
status code.
Based off the downstream commit:
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2038271
Change-Id: I76cde68852fa4963582d57c7dcb9f24de32c6da8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- The USB SPI interface has been split up into write and read stages.
- The packet packing has been transitioned from array based to a
struct.
This was based off the downstream commit:
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2036508
Change-Id: Id3a2a544c1c7e1d969a5157977b8a1c7af18371b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This only sets 3rd CS# bit be asserted during read/write operations.
Tested and confirmed working on 4232H & PicoTap ft2232 programmers
against MX25R6435F & S25FL128S chips.
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Change-Id: Ia0ac14b9a52f251306887500dae3e57d73322157
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This allows multiple 'csgpiol' bits to be set to active state at the
same time. Previously, only one GPIOL could be activated. I have an
use-case such that FT4232H is wired to two different SPI chips, and in
order to select one of them two GPIOLs have to be set.
Now, one can enable any particular GPIOL, for example:
csgpiol=01
would activate GPIOL0 and GPIOL1 at the same time.
The change is backward-compatible with previous csgpiol formatting.
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Change-Id: I645ddaa9852e9995bd2a6764862fda2b2ef0c26b
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Added spireadmode for >= Bolton.
Do not override speed or read mode for >= Bolton if parameter not
specified.
Minor cleanup of sb600spi.c code.
TEST=Manual: deploy on tremblye read flash using various parameters
BUG=b:147665085,b:147666328
BRANCH=master
Change-Id: Id7fec7eb87ff811148217dc56a86dca3fef122ff
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These are helpful usb device accessors and helpers that
are later used for the so-called Raiden debugger programmer.
BUG=b:143389556
BRANCH=none
TEST=builds
Change-Id: Ic928220fc919fe4958c8150e61e11470dac88f13
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The following is a E2E tester for a specific chip/chipset
combo. The tester itself is completely self-contained and
allows the user to specify which tests they wish to preform.
Supported tests include:
- chip-name
- read
- write
- erase
- wp-locking
Change-Id: Ic2905a76cad90b1546b9328d668bf8abbf8aed44
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This modifies CB:23025 further to work with upstream as it is now,
without the syntax changes in the patch chain. I also gave it a new
name since this script is, well, uber.
Since flashrom currently only supports reading/writing ROM-sized files
we can't easily determine a targeted region offset and size except
when a layout file is used. Therefore, some extra arithmetic is needed
in the partial write test and the only modes allowed are clobber mode
and layout mode.
A few other changes:
- Update paths and script name
- Remove write-protect testing support
- Use ROM-sized files only, no region-sized files
- Return error if flashmap or ifd mode are used
Documentation is ported from https://goo.gl/3jNoL7 into a markdown
file and accompanying SVGs. Minor changes were made for clarity and
formatting, and references to write protect testing have been removed
for the time being.
Tested using a Raspberry Pi with a W25Q16
Change-Id: I1af55d5088c54ee33853009797adbd535a506b49
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
As found on the Tesla AP2.5 board.
Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html
Tested with:
flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin
Signed-off-by: Bernhard Urban-Forster <lewurm@gmail.com>
Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Intel Ice Lake systems use an 495 Series Chipset
that behaves compatible to pch300 chips but chip names
are undocumented at this point.
This change was tested in read/write/erase on the Razer
Blade Stealth (late 2019) with intel 1065G7 CPU and
"Ice Lake U Premium PCH".
Change-Id: I6227d32f4476420cf1aeec37ebd4b7648e0b3d15
Signed-off-by: Johanna Schander <git@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/37987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Intel Kaby Lake U (with the 9d4e device id) support is available but
marked not tested.
Tested reading, writing and erasing both internal flash chips on the
Facebook Monolith system with the Intel i3 7100U SoC. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall follow
suit as well.
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Change-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38481
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit e28d75ed7204d7fac2c0fac13978098530b0574e.
This is broken in multiple ways, e.g. pcidev_init() can only return
NULL.
Change-Id: I06242147ba9d3a062d442f645eb0800ef51af19f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Reported-by: Michael Bishop <cleverca22@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38319
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
GCC 4.8 wants an explicit `-std=c99` or something for this to work. It
seems easier to keep the common declaration style.
Change-Id: Ic0819f82169df4d66cc949494229b0749c06e8f6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Miklós Márton <martonmiklosqdev@gmail.com>
Tested reading, writing and erasing the internal flash chip using a
Samsung NP530U3C laptop with an Intel HM76 PCH. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall
follow suit as well.
Change-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/37803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Something to point users to when SMM_BWP might be causing problems.
Change-Id: I394c033e8d4ff96433162f86aefb428d8acf6349
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit adds support for the Adesto AT25SF321 SPI flash chip. Probe
and read operations have been tested via FT2232H interface, but writes
have not been verified.
Datasheet is available at the following URL:
https://www.adestotech.com/wp-content/uploads/DS-AT25SF321_047.pdf
Change-Id: I7410815e063ffe154a97d7ea5881c8eb82025f56
Signed-off-by: Peter Adkins <pete@kernelpicnic.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Don't entagle the code paths for the two NIC classes if it's not necessary.
Only compile tested.
Change-Id: I59164ccf54afbbd64a0598282d13e80ff7fd6fa4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit 61e16e549a52194ac80ef40504f2dc661d1ff99c.
Obviously throws alignment in the table off and changes output
class from `general` to `programmer` for no visible reason.
Change-Id: I864044b9fac6af9cf6a89c053eccdcb36f17c7bd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Tin Can Tools Flyswatter and Flyswatter 2 have a FT2232H
with a JTAG interface wired to port A. The buffers that drive the
JTAG pins need to be enabled with an nOE signal from the
FT2232H ADBUS6 and ADBUS7 pins.
Flyswatter has an ARM-14 JTAG interface and Flyswatter 2 has
an ARM-20 JTAG interface.
Change-Id: I56b1fb76dcda32bb02980cd54a2853506bfc9dfd
Signed-off-by: Russ Dill <Russ.Dill@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Write a pure function for the table validation logic, it is
easier to unit-test.
Change-Id: I07b0f95ec0443fa6a8f54eb93f4a7ea1875cccad
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/37239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
