Tested probe/read/erase/write operations succeed with cros
flashrom on rikku chromebox. Marking as DEP to follow
convention for ME-enabled chipsets.
BUG=b:170906609
BRANCH=none
TEST=Applied patch to cros flashrom and verified that
`flashrom -VV` no longer prints a chipset warning on rikku
Change-Id: I0b4d1dd2b271537faea15856442fe183d9de3318
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This adds support for Spansion 25Fxxxxx chips. These chips
require their own probing logic because the first 6 bytes
returned by RDID must be examined to identify the chip.
New erase functions are required as the chips support multiple
sector layouts, and the default layout must be changed to be
able to erase the entire flash.
Adapted from cros flashrom at
`9c4c9a56b6a0370b383df9c75d71b3bd469e672d`.
BUG=b:153800073
TEST=builds
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Change-Id: I2d23f9c36ce8b2959807fbeee7f60e02444e3763
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Allows drivers to register a callback function to reset the
chip state once programming has finished. This is used by
the s25f driver added in a later patch, which needs to change
the chip's sector layout to be able to write to the entire flash.
Adapted from cros flashrom at
`9c4c9a56b6a0370b383df9c75d71b3bd469e672d`.
BUG=b:153800073
BRANCH=none
TEST=builds
Change-Id: I2a522dc1fd3952793fbcad70afc6dd43850fbbc5
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47276
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Align with the properly tab indented comment on the CrOS
Flashrom side to make things consisent.
Change-Id: I09605bfec203d294077f298f8619bbc7d10cc68a
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/48204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Unfortunately raiden_debug was upstreamed with a slightly
incorrect name of "raiden_debug" whereas in ChromiumOS
it is known as "raiden_debug_spi" and so correct this to
align. This avoids confusion and divergence for a unified
future.
Change-Id: I0eca35863403c5d4adbe19b31801e8dfa072006f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/48106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Unfortantly raiden_debug was upstreamed with a misnaming
of the CONFIG_ make param that introduces unnecessary divergence.
Rename to 'CONFIG_RAIDEN_DEBUG_SPI' as-is downstream.
Change-Id: I07c03647c329286bb223e4dae4665704e508db2c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/48105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Have 'determine_generation()' explicitly return 'amd_gen'
and then pass the state into what requires it, thus making
the code more pure, easier to read and more unit-testable.
Change-Id: I99fbad9486123c6b921eab83756de54a53ddfa7a
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
This upstreams a ChromiumOS feature that allows the user
of the dummyflasher spi master to either fill with 0x00
or 0xff in the fake flash content by way of a spi master
param.
BUG=b:140394053
BRANCH=none
TEST=none
Change-Id: I37c6dee932e449201d8bbfb03ca6d139da3cb6a2
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Make use of the reneterent framework by moving singleton static
state out of the global life-time and into a per-spi_master basis.
This allows for the wbsio_spi master to be reneterent and its internal
state's life-time to be correctly handled by Flashrom's core dispatch
logic.
BUG=none
TEST=builds
Change-Id: Ic97fa41daf26f27b68ced11ddc2a4da91d18f68e
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47854
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reshuffle file with no semantic changes, this avoids unnecessary
prototypes for static member functions as to pave the way for further
cleanups as well as an easier to parse implementation.
BUG=none
TEST=builds
Change-Id: Iae9426b6a8ba6a824f7d7e9aaf9f8174b044d04c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested reading, writing and erasing the internal flash chip using an HP
Elite 8200 mainboard with an Intel Q67 PCH. However, since ME-enabled
chipsets are marked as DEP instead of OK, this one shall also be.
Change-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reshuffle file with no semantic changes, this avoids unnecessary
prototypes for static member functions as to be an easier implementation
to parse.
BUG=none
TEST=builds
Change-Id: If3970d850989eafc59cec9158ecfcdafc7a8caea
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reshuffle file with no semantic changes, this avoids unnecessary
prototypes for static member functions as to be an easier implementation
to parse.
BUG=none
TEST=builds
Change-Id: Ided41c6c64376e0cddeb17b936773a86c36d5f72
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
The local state inhabited within the state tracker has now obvious scope
and therefore we can drop the redundant prefix for readability.
BUG=b:173477683
TEST=builds
Change-Id: Ic1c9647ef640152417a66dbb411554b83e30ad75
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Make use of the reneterent framework by moving singleton static
state out of the global life-time and into a per-spi_master basis.
This allows for the it87spi master to be reneterent and its internal
state's life-time to be correctly handled by Flashrom's core dispatch
logic.
BUG=b:173477683
TEST=builds
Change-Id: I6e9c3e6f12e51e456ee237c389cc326c64a71999
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reshuffle file with no semantic changes, this avoids unnecessary
prototypes for static member functions as to pave the way for further
cleanups as well as an easier to parse implementation.
BUG=b:173477683
TEST=builds
Change-Id: I94b169d19cb29336bb9cb4c16d0efee15b1e14c2
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47661
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reshuffle file with no semantic changes, this avoids unnecessary
prototypes for static member functions as to pave the way for further
cleanups as well as an easier to parse implementation.
BUG=b:172876667
TEST=builds
Change-Id: Idf4241c92d90c28dd4f4ec3b7d66bda50801385a
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47657
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modified to be pch7 over pch6 as per-coreboot and review
comments.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47090
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both requires PCI port I/O and hence works only on x86.
TEST=builds on Ubuntu for Raspberry Pi
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I69e1fbd87819b0b6370f31e9ee4c474500fb3759
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Programmer enumerators and their corresponding programmer_table entries
need to be aligned. This was not the case for MEC1308 and ENE_LPC.
Their configs were not enabled by default until commit 26fde5b0b067
("ene_lpc,mec1308: Fix entry-points to be explicit")/CL:2488823,
allowing this issue to go unnoticed. The particular symptom of the
mismatch was internal_init() trying to init linux_mtd instead of
linux_spi.
BUG=b:172668501
TEST=flashrom -p host on gale
BRANCH=None
Original-Change-Id: I2e9d3df6a6fd6d5d8e3a5a13ee56f5997b10ea52
Original-Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: I8e7a57b7c30e2dd2306d6fe7268eee8bb9d0c8a5
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47353
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Victor Ding <victording@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of hard coding the test procedure on qa.coreboot.org, allow
running a script in the repo instead. The server is already adapted
to do that, so once there's a test_build.sh file in the toplevel
directory, it's run in place of the default operation.
The content of this change mirrors the default operation exactly so
should serve as a good starting point.
The script is executed in an encapsulate[0] context with the workspace,
/tmp and $HOME/.ccache writable, everything else read-only and
network disabled.
It should return 0 on success, anything else on failure, as is normal
for UNIX processes.
[0] https://review.coreboot.org/cgit/encapsulate.git
Change-Id: I37a8e925d1b283c3b8f87cb3d0f1ed8920f2cf95
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Make use of the JEDEC_CE_{60,62,C7} defined constants of
the op-codes in each of the spi_simple_write_cmd() calls
to assist in readability.
V.2: Squash in JEDEC_BE_{52,C4,D7,D8,50,81} && JEDEC_SE.
Both 'S'ector and 'B'lock 'E'rasers now use the consts in
spi.h.
BUG=none
BRANCH=none
TEST=builds same object.
Change-Id: I1876781672fe03302af4a6ff8d365f2e6c3b6f13
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47005
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This uses the JEDEC_WREN_OUTSIZE define in the spi_simple_write_cmd()
helper function to improve readability.
BUG=none
BRANCH=none
TEST=builds same object
Change-Id: I1b5ede4435ba014320fa8cf9490dc23cdfba4fd6
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shiyu Sun <sshiyu@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Looks like the year should be 2010 based on cros git history.
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Change-Id: I7c27e682bd09f7b1ba0398dc231b9360aed1c26b
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This makes it again easier to parse internal.c by consolidating
some processor wraps and labeling the ends of others.
BUG=none
BRANCH=none
TEST=builds
Change-Id: I32fb1a3fff7afa671f08fb2cc2ad406772f5e10f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46815
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LSPCON and MST do not depend on libusb.
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: If6db3a318aca349fc1ccd343d3d6d47b809eac8e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch fixes a few bugs that two patches ( `3149822cd45cb2e5841e15d648783748ba1b2ec6` && `3b8fe0f8e907c0ba9f7c7935e950f3e1538d427f`) brought:
* Check the presence of 'size' param only if the emulate is VARIABLE_SIZE.
* Initialize 'flash->st->par.data' in dummy_init() so that it can probe the VARIABLE_SIZE emulator correct in probe_variable_size().
* Replace atoi() with strtol().
* Revise man page to describe how to use the VARIABLE_SIZE emulation target.
TEST:
$ flashrom -p dummy:image=dummy.bin,emulate=VARIABLE_SIZE,size=16777216 \
-w ${IMG} -V -f
...
Verifying flash... VERIFIED.
Writing dummy.bin
$ flashrom -p dummy:image=dummy.bin,emulate=VARIABLE_SIZE -w ${IMG} -V -f
...
dummy_init: the size parameter is not given.
Unhandled programmer parameters (possibly due to another failure): image=dummy.bin,
Error: Programmer initialization failed
$ flashrom -p dummy:image=dummy.bin,emulate=SST25VF040.REMS -c SST25LF040A -w ${IMG}
...
Erasing and writing flash chip... Erase/write done.
Verifying flash... VERIFIED.
$ man flashrom
...
* Dummy vendor VARIABLE_SIZE SPI flash chip (configurable size, page write)
Example: flashrom -p dummy:emulate=SST25VF040.REMS
To use VARIABLE_SIZE chip, size must be specified to configure the size of the flash chip as a power of two.
Example: flashrom -p dummy:emulate=VARIABLE_SIZE,size=16777216,image=dummy.bin
...
Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: Ie6481943a831b946a91b643b4d79e684c27e48b8
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Both depend on functions from chipset_enable.c and board_enable.c, which
require libpci.
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I9505d7f18f4781a264e29e9667b717c061ba33b8
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46812
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This line gets printed even when not using dummyflasher at all. Drop it.
TEST=Check that no spurious error message appears with ft2232_spi.
Change-Id: I1a81a735db391357d1b6ee6f3e9844255efd0e19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Port from the ChromiumOS fork of flashrom.
Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This just makes internal.c at bit easier to parse and helps
the read get a view of all the singleton state in one go.
BUG=none
BRANCH=none
TEST=builds
Change-Id: Id4109dfb17f63d80fb3fb3f2a1d0ab54d9eddc6e
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This just makes internal.c a little easier to parse and avoids
some fn prototypes on the mental stack.
BUG=none
BRANCH=none
TEST=builds
Change-Id: I693e30068e6a53b5fc161d895af451540650a8fe
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both use INB/OUTB and hence should be marked as NEED_RAW_ACCESS in the
makefile.
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I6fafd9f59d06f60e9491e3e059c1205d48d8232e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46811
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Seems to be dead code with no call sites.
BUG=none
BRANCH=none
TEST=builds
Change-Id: Ic9f33415b8a357916891cb2006612cbf5e6aa559
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
This is needed to avoid attempt entering ISP mode multiple
times. The ISP mode can only exit after a reset, so once the
reset MCU parameter is set to 0, the device will not able to
exit from ISP mode and hence shouldn't enter ISP again on
the next operation.
Without exit ISP mode, the device data, like firmware version,
will not show the correct value, this param will also help
to identify this situation.
BUG=b:152558985,b:148745673
BRANCH=none
TEST=build and run:
$ flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=0,enter-isp=1 \
-l layout -i PARTITION1:fw -w
$ flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=0,enter-isp=0 \
-l layout -i FLAG1:flag -w
then either reset computer to allow update to take effect, or:
$ flashrom -p realtek_mst_i2c_spi:bus=x,reset-mcu=1,enter-isp=0 \
--flash-size
to trigger the update.
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: I58931ac8b42ab55829f102d243aea6fcfd632e3e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The memory for the `param` string is aliased by `dualbiosindex_suffix`.
Moreover, `errno` could have been modified by the call to `free()`.
Therefore, only free the former when there are no more uses of either.
Change-Id: I79f18f6077c77c0cbb8bfa431e17f9b079f11c95
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With pciutils 3.7.0, flashrom is unable to match any PCI devices by
vendor/device ID because the vendor_id and device_id fields of struct
pci_dev are not filled in.
Call pci_fill_info() to request these identifiers before trying to match
them against the supported device list.
The pciutils ChangeLog for 3.7.0 mentions that the documentation and
back-end behavior for pci_fill_info() was updated; it seems that a call
to pci_fill_info() was always intended to be required, but some backends
(such as the sysfs one used on Linux) would fill the identifier fields
even when not requested by the user. The pci_fill_info() function and
the PCI_FILL_IDENT flag have been available for all versions of pciutils
since at least 2.0 from 1999, so it should be safe to add without any
version checks.
With this change, reading/writing a nicintel_spi boot ROM is successful.
Signed-off-by: Daniel Verkamp <dverkamp@chromium.org>
Change-Id: Ia011d4d801f8a54160e45a70b14b740e6dcc00ef
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46310
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Here we provide a helper function to allow indexing MCU configuration
registers. The 0x9F port allows access to these MCU configuration
registers followed by the high and then low bytes of the register
address we wish to index written into 0xF5 or 0xF4 respectively, a
read or write can then be made via 0xF5.
For the configuration of GPIO pins on the chip, there are two relevant
register address, 0x104F for pin direction (sink input or push-pull
in-out) configuration and 0xFE3F for pin data values (1 to push-pull
and 0 to sink). The reference design uses GPIO 88 to strap the
write protection pin and so we provide a function that allows the call
site to toggle this state and therefore de-assert hardware write
protection of the external spi flash.
BUG=b:152558985,b:148745673
BRANCH=none
TEST=builds && verified the write protection get disabled.
Change-Id: I1aed0086f917e31bebb51857ad5cce138158fe82
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46089
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
default_spi_read() calls spi_read_chunked() with the correct
max_read value of 3 set in the spi master struct.
Change-Id: I199c81e1ba501e86dbfb7cf18e2d1556e30db62e
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46233
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
