The JEDEC SFDP specification JESD216A (1.5) adds five new DWORDs to the
Basic Flash Parameter Table. Later versions of the spec add even more
fields. This increases the table being read from 36 bytes to currently
64 bytes and makes flashrom bail out for any SFDP version >= 1.5 due to
a static table length check.
This was discovered on a GigaDevice GD25B127DSIGR from 2021 with SFDP
revision 1.6, while another flash of the same model from 2020 with SFDP
revision 1.0 was detected fine by flashrom.
GD25B127DSIGR - 2020 version:
Probing for Unknown SFDP-capable chip, 0 kB: SFDP revision = 1.0
SFDP number of parameter headers is 2 (NPH = 1).
SFDP parameter table header 0/1:
ID 0x00, version 1.0
Length 36 B, Parameter Table Pointer 0x000030
GD25B127DSIGR - 2021 version:
Probing for Unknown SFDP-capable chip, 0 kB: SFDP revision = 1.6
SFDP number of parameter headers is 2 (NPH = 1).
SFDP parameter table header 0/1:
ID 0x00, version 1.6
Length 64 B, Parameter Table Pointer 0x000030
...
Length of the mandatory JEDEC SFDP parameter table is wrong (64 B),
skipping it.
The specification says that changes of the minor SFDP revision will
maintain compatibility. Thus, simply check for the minimal required
table length, which is 16 bytes for legacy Intel pre-SFDP and 36 bytes
for SFDP.
Change-Id: Id84cde4ebc805d68e2984e8041fbc48d7ceebe34
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The Makefile recently gained finer-grained programmer dependency lists
allowing it to track which enabled programmers assume various things
about the system, like availability of libraries or the CPU
architecture. This change implements the same changes in the Meson
configuration file.
This fixes a number of programmers to correctly build on non-x86
systems, because they were previously misclassified as dependent on x86
architectural features but actually only used PCI.
BUG=none
TEST=meson build succeeds on both x86 and ARM
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Iae93111fd48865f3fe8dd0eb637349b9a0c4affc
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
The changes to hwaccess in commit 49d758698a0dd166679c48b1a2785e50e9b0cc83
cause build failure on non-x86 systems because the hwaccess_x86_*
headers are included in some files that are built for all platforms
(particularly those in the internal programmer) and those headers in
turn include <sys/io.h> which only exists on x86.
This change avoids including those headers on non-x86 platforms so
the internal programmer can be built without errors.
The comment on the stub implementation of rget_io_perms() is also
modified to remove references to non-x86 platforms, since that file is
only built on x86 now.
BUG=None
TEST=meson build succeeds for both x86 and ARM targets
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I20f122679c30340b2c73afd7419e79644ddc3c4e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61194
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Aspire towards a goal of making cli_classic more of just
a user of libflashrom than having quasi-parallel paths in
flashrom.c
This converts the do_read() provider wrapper into a pure
libflashrom user.
BUG=b:208132085
TEST=`$ sudo ./flashrom -p internal -r /tmp/bios.bin`
TEST=`$ sudo ./flashrom -p internal -l /tmp/layout -i FOO -r /tmp/foo.bin`
Change-Id: Id2addadb891c482ee3f69da806062d7a88776675
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Inline emergency_help_message() to cli_classic call site.
This leaves do_erase() a redudant wrapper and moves us a step
closer to cli_classic as a pure libflashrom user by using
flashrom_flash_erase().
BUG=b:208132085
TEST=`flashrom -E`
Change-Id: I8566164e7dbad69cf478b24208014f10fb99e4d0
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This change fixes a bug on handling the extract operation. The extract
operation reads out the layout regions to filenames corresponding to the
respective layout region names. read_flash_to_file() does this work via
write_buf_to_include_args(). This change makes the call to
write_buf_to_file() optional as it is still required for -r (read
operation) but not for -x (extract operation).
BUG=b:209512852
TEST=flashrom -x
Fixes: commit ce983bccaab450d358854494f15c2d8a1846d56b
Change-Id: Ibc9a4e2966385863345f06662521d6d0e4685121
Signed-off-by: Daniel Campello <campello@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
These targets are all called together. No need to have them individual.
Change-Id: Ic76f923bca2beb6f95b8ea0cced4569b07e9b9ba
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use the order in which the targets get executed.
Change-Id: Ic45c2fc98c679ac7be4ee2860d72b517b8b67a17
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use `make HAS_LIBPCI=yes/no` to override the pkg-config detection and
`CONFIG_LIBPCI_CFLAGS` and `CONFIG_LIBPCI_LDFLAGS` to set cflags and
ldflags manually. The optional dependency of libpci libz, is
automatically handled by pkg-config.
Change-Id: I21b4a261b34b7e688635fc6e20b7beebfa64c7ed
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Let programmer only depend on the kind of hardware access method they
really need. Libpci no longer depends on all hardware access types since
each programmer handles this individually.
Change-Id: I5bdafaa3c5023ad6c4a695493eeddf11bc148085
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The mmio_le/be_read/writex functions are used for raw memory access.
Bundle them with the physmap functions.
Change-Id: I313062b078e89630c703038866ac93c651f0f49a
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As a part of effort to convert command line (and everything else)
to be libflashrom users, chip tests need to be converted as well.
TEST=ninja test
Change-Id: I965598cfa74e3fb7d0780ad34491f4057617691e
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
As a part of effort to convert command line (and everything else)
to be libflashrom users, chip tests need to be converted as well.
TEST=ninja test
Change-Id: I4493d4f269595783830c39a720b0a8963eab9daa
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
As a part of effort to convert command line (and everything else)
to be libflashrom users, chip tests need to be converted as well.
TEST=ninja test
Change-Id: I38529a6b4d79882f50068b3628089b178dbe0a50
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
dediprog_bulk_read_poll()'s finish argument allows it to be used in two
distinct cases: where dediprog_bulk_read_poll will be called as part of
a loop (finish=0) and where dediprog_bulk_read_poll should wait for all
outstanding transfers to finish (finish=1). In both cases,
dediprog_bulk_read_poll() calls libusb to process events with a 10
second timeout.
After dediprog_spi_bulk_read() has queued the last transfers, it calls
dediprog_bulk_read_poll() with finish=0 when it should be finish=1.
finish=0 just happens to work because frequently the transfers finish in
the 10 second timeout.
Signed-off-by: Rick Altherr <rick@oxidecomputer.com>
Change-Id: If7cb541742c8620358c8e04275d8316131b2d1ab
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Make the linux_mtd driver treat any negative return value from the
MEMERASE ioctl as an error. Previously it only treated -1 as an error.
BUG=b:213561594,b:210973586,b:182223106
BRANCH=none
TEST=builds
Change-Id: I40cfbdee2ab608fbe6c17d9cac6ec53ff224d9a4
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
While using the libflashrom API to read specific regions
there is no currently no general way to find the offset
into the read buffer of the expected region.
flashrom_layout_include_region() probably should have
returned the region offset and size if it was included.
However to avoid a change in API signature we can instead
hoist up get_region_range() into the API to be called after.
BUG=b:207808292
TEST=`make` && tested in porting cbfstool use-case.
Change-Id: I8cf95b5eaec943a51d0ea668f26a56bf6d6b4446
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
The it8212 programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: Iab859fb6be6cab094c9c6ce4b3e8eac0e5ff84ab
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60869
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The satasii programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: I54d65561ff024d3c181d11c6518a4612c2ab0399
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60848
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ogp_spi programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: I1f3f34e33f77159fa0cdea150e1f408ce9d943f0
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The nicintel_spi programmer does not use x86 IO Ports. Remove the
dependency to it.
Change-Id: I3e7451eceb1f01de21da934c9559dbf2f06e7e54
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60846
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The nicintel_eeprom programmer does not use x86 IO Ports. Remove the
dependency to it.
Change-Id: I5fd42572fd29f5d7fd749c2836eac3e68c947946
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60845
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The nicintel programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: Ibe609ff8f8fdbdf2a7de8e1922325ca4ad56a9e7
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60844
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The gfxnvidia programmer does not use x86 IO Ports. Remove the
dependency to it.
Change-Id: I1f0341390ccb698bc435760f4ead7de54e429a6e
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60843
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The drkaiser programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: I86bad947298a1166ff1e768f7d0b75a90e574696
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60842
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The atavia programmer does not use x86 IO Ports. Remove the dependency
to it.
Change-Id: I1fa866b3b07adf5f7a51d58f53d6cad1f88d7210
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60841
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List all programmers which depend on the respective hwaccess features.
This is the base for a precise feature selecting in the build system.
Change-Id: I588f698780b5acd65084346bcef781cbfd1203ea
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Line up physmap with the other hwaccess related code.
Change-Id: Ieba6f4e94cfc3e668fcb8b3c978de5908aed2592
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Allow x86 msr related code to be compiled independent from memory
mapping functionality. This enables for a better selection of needed
hardware access types.
Change-Id: Idc9ce9df3ea1e291ad469de59467646b294119c4
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Allow port I/O related code to be compiled independent from memory
mapping functionality. This enables for a better selection of needed
hardware access types.
Change-Id: I372b4a409f036da766c42bc406b596bc41b0f75a
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Split the include of hwaccess and libpci. There is no need to have pci.h
included in hwaccess.
Change-Id: Ibf00356f0ef5cc92e0ec99f8fe5cdda56f47b166
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use `make HAS_LIBUSB1=yes/no` to override the pkg-config detection and
`CONFIG_LIBUSB1_CFLAGS` and `CONFIG_LIBUSB1_LDFLAGS` to set cflags and
ldflags manually.
Change-Id: I4f24be647d25dde24c41514f8964b7134205867c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use `make HAS_LIBJAYLINK=yes/no` to override the pkg-config detection
and `CONFIG_LIBJAYLINK_CFLAGS` and `CONFIG_LIBJAYLINK_LDFLAGS` to set
cflags and ldflags manually.
Change-Id: I99df547046bb9820ab502f89f6d4452c1bc0cfd4
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since the NI-845x is a Windows only proprietary library, disable it by
default. Use `HAS_LIB_NI845X=yes` to enable it. The default search path
is `${PROGRAMFILES}\National Instruments\NI-845x\MS Visual C` and can be
overwritten by `CONFIG_NI845X_LIBRARY_PATH`. Use
`CONFIG_LIB_NI845X_CFLAGS` and `CONFIG_LIB_NI845X_LDFLAGS` for setting
the cflags and ld flags manually.
Change-Id: I918c3605a5ac168708a6a10fd92ee2a1aae9729b
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use `make HAS_LIBFTDI1=yes/no` to override the pkg-config detection and
`CONFIG_LIBFTDI1_CFLAGS` and `CONFIG_LIBFTDI1_LDFLAGS` to set cflags and
ldflags manually.
Change-Id: I41f5186d9f3e063c12c8c6eea888d0b0bf534259
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It was absent from the list of emulated chips.
Change-Id: I50f6cd6c5d853d6c70921e8027ada52d27982708
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This section is rather outdated and should be dispensed with.
Change-Id: Id7e0ce412901ccb27124a9958d5ef214ab289518
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
I have successfully tested it with FT2232H-programmer.
Change-Id: Ia9a32146b225eca66e9a6bfef45be5f2b24aef46
Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch adds a test for raiden_debug_spi and lots of libusb wraps.
libusb.h becomes required for tests to build and run, since new tests
are using libusb structs in depth and opaque symbols not sufficient
anymore.
BUG=b:181803212
TEST=builds and ninja test
Change-Id: I880a8637ab02de179df9169c1898230bce4dc1c7
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/57918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
__xstat and __fxstat variants of stat/fstat are invoked under
chromium chroot. For all existing tests it is sufficient for
stat/fstat to "do nothing, return 0", so new wraps do just that.
Test which needs __xstat: linux_mtd lifecycle.
Tests which need __fxstat:
read_chip_test_success
read_chip_with_dummyflasher_test_success
write_chip_test_success
write_chip_with_dummyflasher_test_success
Without this patch tests above fail under chromium chroot.
BUG=b:181803212
TEST=running tests on three different environments,
1) stat64/fstat64 (ninja tests in upstream tree)
2) stat64/fstat64 (ninja tests in chromium tree)
2) __xstat64/__fxstat64 (emerge with tests in chromium tree)
Change-Id: I4c5c243acde09dc5bb6b2a14042fcd23a49707db
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and
detects as unknown chipset compatible with 300 series chipset. Add a
new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to
CHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,
ICCRIBA is no longer present n descriptor content so a new union has
been defined for new fields and used in descriptor guessing.
freq_read field is not present on Tiger Lake, moreover in CannonPoint
and Comet Point this field is used as eSPI/EC frequency, so a new
function to print read frequency has ben added. Finally Tiger lake
boot straps include eSPI, so a new bus has been added for the new
straps.
TEST=Flash BIOS region on Intel i5-1135G7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Flash context used to be named `flash` which was missing the
context part of it. Now it is renamed into flashctx for clarity.
BUG=b:181803212
TEST=ninja test
Change-Id: I3f4d9c4fe85752e16bab71ad22b0135a96cac28a
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
