New IDs taken from Intel's patches for the Linux kernel.
Also, refine original Lynx Point naming etc.
Corresponding to flashrom svn r1656.
Based on the chromiumos patch
Change-Id: I303a05baa80e4449e70d20adf78ebc7128b88d8e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Also, unify all outputs of "Warning:" and "Error:" to use normal
capitalization instead of mixing it with all capitals.
Corresponding to flashrom svn r1643.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Idwer Vollering <vidwer@gmail.com>
Tested Mainboards:
OK:
- Foxconn P55MX
http://www.flashrom.org/pipermail/flashrom/2012-October/010002.html
Tested flash chips:
- Eon EN25F64 to PR (+PR)
http://paste.flashrom.org/view.php?id=1426
- Macronix MX25L1005 to PREW (+PREW)
http://www.flashrom.org/pipermail/flashrom/2012-October/010004.html
- Set SST39VF512 to PREW (+W)
http://www.flashrom.org/pipermail/flashrom/2012-September/009958.html
Tested chipsets:
- Z77 (only reading was really tested)
Miscellaneous:
- Fix ft2232_spi's parameter parsing.
- Fix nicrealtek's init (always segfaulted since r1586 oops).
- Add another T60 variant to the laptop whitelist.
- Improve message shown when image file size does not match flash chip
- Refine messages regarding the flash descriptor override strap according
to the findings by Vladislav Bykov on his P55MX.
- Fix the ID of EN25F64.
- Demote and clarify debug message in serprog_delay().
- Minor other cleanups.
Corresponding to flashrom svn r1613.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
We made a first step into this direction in r1405, but failed to
notice that there was already an extended patch by Jonathan which
was refined to become this one.
Allows the removal of board_shuttle_fn25 (which was also intended to be
used on the ASUS A8N-SLI Deluxe, but this was never tested).
Corresponding to flashrom svn r1593.
A previous iteration was tested on CK804 and
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
which was then
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Rebasing, refining and making errors non-fatal is
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This patch also changes semantics: previously failing to set this was interpreted as
a fatal error by enable_flash_ck804 and enable_flash_mcp55 although the output
indicated otherwise. Also, in enable_flash_nvidia_nforce2 there was no check
if settings the bit succeeds.
Now all methods check for success and return ERROR_NONFATAL on failure.
Corresponding to flashrom svn r1592.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This patch just fixes a limited number of bits not conforming to c99 by using
- __asm__ instead of just asm
- {0} instead of {} for struct initialization
- h_addr_list[0] instead of h_addr to access the host address in
struct hostent
- #include <strings.h> where needed (for ffs and strcasecmp)
Based on a previous patch by Carl-Daniel.
Corresponding to flashrom svn r1585.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This is based on chromiumos commit a5f4e82c59d6bcaf06b94623e5516d1db8cb843a.
http://git.chromium.org/gitweb/?p=chromiumos/third_party/flashrom.git;a=commit;h=a5f4e82c59d6bcaf06b94623e5516d1db8cb843a
See also http://www.flashrom.org/pipermail/flashrom/2011-November/008191.html
Besides disabling the SMM protection this also fixes something that bothered
me for a long time: the content of BIOS_CNTL was shown before we try to modify
it. This is usually not what interests us and contradicts other outputs.
With this patch we try to set the write enable and disable the SMM protection
first and show the state of BIOS_CNTL afterwards.
We now return an error only if the write enable is not set (which should be
equivalent to the previous behavior on sane hardware, but it seems to be
'more correct' and makes the code clearer to do this explicitly).
Corresponding to flashrom svn r1582.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Helge Wagner's patch that added VIA VX900 chipset support made me look
closer at the datasheets which led to some concise documentation about
newer VIA chipsets: http://flashrom.org/VIA
Based on that this patch adds full support for VX800/VX820, VX855/VX875
and VX900, including SPI and LPC. VT8237S was not changed (SPI support
only) because there is no public datasheet and it is not clear how to
distinguish between LPC and SPI strapping and investigations in (NDAed)
documents have not brought up anything conclusively.
enable_flash_vt823x could probably be enhanced too due to various
ignored LPC options of the chipset.
Corresponding to flashrom svn r1578.
Signed-off-by: Helge Wagner <Helge.Wagner@ge.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
I looked at the datasheet to be sure that the strap names (SPI, PCI,
LPC) are the same as on the series 5 and 6 chipsets.
Corresponding to flashrom svn r1553.
Signed-off-by: Helge Wagner <Helge.Wagner@ge.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Move hwaccess.h #include from flash.h to individual drivers.
libflashrom users need flash.h, but they do not care about hwaccess.h
and should not see its definitions because they may conflict with
other hardware access functions and #defines used by the libflashrom
user.
Corresponding to flashrom svn r1549.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested on Bifferboard.
Corresponding to flashrom svn r1489.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
All programmers are now calling programmer registration functions and
direct manipulations of buses_supported are not needed/possible anymore.
Note: Programmers without parallel/LPC/FWH chip support should not call
register_par_programmer().
Additional fixes:
Set max_rom_decode.parallel for drkaiser.
Remove abuse of programmer_map_flash_region in it85spi.
Annotate several FIXMEs in it85spi.
Corresponding to flashrom svn r1463.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Based on the new opaque programmer framework this patch adds support
for Intel Hardware Sequencing on ICH8 and its successors.
By default (or when setting the ich_spi_mode option to auto)
the module tries to use swseq and only activates hwseq if need be:
- if important opcodes are inaccessible due to lockdown
- if more than one flash chip is attached.
The other options (swseq, hwseq) select the respective mode (if possible).
A general description of Hardware Sequencing can be found in this blog entry:
http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/
Besides adding hwseq this patch also introduces these unrelated changes:
- Fix enable_flash_ich_dc_spi to pass ERROR_FATAL from ich_init_spi.
The whole error handling looks a bit odd to me, so this patch does
change very little. Also, it does not touch the tunnelcreek method,
which should be refactored anyway.
- Add null-pointer guards to find_opcode and find_preop
to matches the other opcode methods better:
curopcodes == NULL has some meaning and is actively used/checked in
other functions.
TODO: adding real documentation when we have a directory for it
Corresponding to flashrom svn r1461.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The type member is enough most of the time to derive the wanted
information, but
- not always (e.g. ich_set_bbar),
- only available after registration, which we want to delay till the
end of init, and
- we really want to distinguish between chipset version-grained
attributes which are not reflected by the registered programmer.
Hence this patch introduces a new static variable which is set up
early by the init functions and allows us to get rid of all "switch
(spi_programmer->type)" in ichspi.c. We reuse the enum introduced
for descriptor mode for the type of the new variable.
Previously magic numbers were passed by chipset_enable wrappers. Now
they use the enumeration items too. To get this working the enum
definition had to be moved to programmer.h.
Another noteworthy detail: previously we have checked for a valid
programmer/ich generation all over the place. I have removed those
checks and added one single check in the init method. Calling any
function of a programmer without executing the init method first, is
undefined behavior.
Corresponding to flashrom svn r1460.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
- introduce a new variable 'wanted' that is used instead of 'new'
- use 'new' for the actual value contained in BIOS_CNTL after we tried to write it
- rephrase the warning which now also includes the old and new values besides the wanted one
Corresponding to flashrom svn r1435.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Intel's Tunnel Creek chipset supports both an SPI and an LPC bus. Set the
chipset table entry for Tunnel Creek to the new function
enable_flash_tunnelcreek(), which will read the hardware straps and return
support for the bus that has been used for booting. This function uses
ich_init_spi() with ich_generation set to 7 for initializing the SPI bus
if necessary.
SPI functionality tested on actual hardware, Tunnel Creek LPC interface not
tested yet (missing hardware for that).
Log file / success report:
http://www.flashrom.org/pipermail/flashrom/2011-September/007823.html
Corresponding to flashrom svn r1430.
Signed-off-by: Ingo Feldschmid <ifel@msc-ge.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
The meaning of the bits involved has changed several times in the past.
This patch takes these changes into account and hence fixes the output of the
pretty printing of GCS on all SPI-supported Intel chipsets that are not ICH7 or
NM10 (the latter were unaffected, because the defaults were correct).
This patch also allows to differentiate Ibex Peak and Cougar Point chipsets from
the earlier chipset series (ICH10) by adding new wrapper functions that set
"ich_generation" to 11 and 12 respectively. This should not change behavior
outside of enable_flash_ich_dc_spi, because the code path for
ich_generation >=9 is equal.
alternatively we could just remove the pretty printing of GCS and just output
the bits involved. i would like to keep the pch differentiation anyway though,
because i feel it will become handy in the future.
tested on my QS57-based thinkpad (probe + partial read)
Corresponding to flashrom svn r1423.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
AMD Hudson has different vendor/device IDs than AMD SBx00, handle
that properly.
Corresponding to flashrom svn r1422.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- Mixing uninitialized and initialized local variables leads to
confusion.
- ft2232_spi error cases should have gotten some error handling, and
that's the reason the curly braces were there.
- Fixing typos/wording in some places would have been nice given that
those places were touched anyway.
Corresponding to flashrom svn r1413.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
It is based on Joshua Roys' RE.
http://www.flashrom.org/pipermail/flashrom/2011-August/007504.html
Corresponding to flashrom svn r1408.
Tested-by: Márton Miklós
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
The OEM BIOS on the EPoX EP-8PA7I and a number of other boards clear
byte 0x92 in the LPC bridge configuration space. Do the same for
all CK804 chips, assuming this to be some sort of chipset-generic
write-enable.
Currently the same chipset enable is used for MCP51 (nForce 430).
There have been reports of successful writes with its variations
(e.g. A8N-LA (Nagami-GL8E)), but they were not tagged as OK. Due to
the new "unsupported chipset"-message we will get success reports in
the case this patch does not break anything on the MCP51-based boards.
See also:
http://www.flashrom.org/pipermail/flashrom/2011-July/007252.htmlhttp://patchwork.coreboot.org/patch/3176/
Corresponding to flashrom svn r1405.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Joshua Roys <roysjosh@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Corresponding to flashrom svn r1403.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Also, indentation fixes, e.g. due to conversion to msg_*, use ARRAY_SIZE
where possible, wrap overly long line, etc.
Compile-tested. There should be no functional changes.
Corresponding to flashrom svn r1397.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
It's shorter to type, and we have less problems with the 80 column limit.
Corresponding to flashrom svn r1396.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
The code took 32 bits of input and wrote them to an 48 bit register,
duplicating some values.
Document the fwh_idsel= parameter in the man page.
Corresponding to flashrom svn r1389.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Old output:
Calibrating delay loop... OK.
Found chipset "Intel QS57", enabling flash write... OK.
This chipset supports the following protocols: FWH, SPI.
new non-verbose output for tested chipsets:
Calibrating delay loop... OK.
Found chipset "Intel QS57". Enabling flash write... OK.
This chipset supports the following protocols: FWH, SPI.
new non-verbose output for untested chipsets:
Found chipset "Intel QS57".
This chipset is marked as untested. If you are using an up-to-date version
of flashrom please email a report to flashrom@flashrom.org including a
verbose (-V) log.
Enabling flash write... OK.
This chipset supports the following protocols: FWH, SPI.
Corresponding to flashrom svn r1379.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This was deliberately disabled until now, but seems to work well enough.
Corresponding to flashrom svn r1372.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
As defined by Intel 6 Series Chipset and Intel C200 Series Chipset
Specification Update; document number 324646-006, May 2011.
Corresponding to flashrom svn r1344.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This patch combines three previously posted patches in a revised form.
one is even stolen from Stefan Reinauer (remove umlauts from man page).
Corresponding to flashrom svn r1317.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Corresponding to flashrom svn r1295.
Signed-off-by: John Schmerge <jbschmerge@gmail.com> for Devon IT
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This patch fixes the "using plain integer as NULL pointer" warnings
generated by running sparse on the flashrom source.
Corresponding to flashrom svn r1255.
Signed-off-by: Peter Huewe <peterhuewe@gmx.de>
Acked-by: Mathias Krause <mathias.krause@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
The address part was using a bit of the size, the size was missing the
upper bit, was off by 1023 bytes and included the protection bits.
Corresponding to flashrom svn r1250.
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
