It initializes an empty layout. Currently the maximum number of entries
has to be specified, which will vanish once we use dynamic allocation
per entry.
We replace the two special cases `single_layout` and `ich_layout` with
dynamically allocated layouts. As a result, we have to take care to
release the `default_layout` in a flashctx once we are done with it.
Change-Id: I2ae7246493ff592e631cce924777925c7825e398
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Adds a region to an existing layout, as long as there is space.
Change-Id: I50d473d0d5d1fb38bd6f9ae3d7127e9ea66a94e1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33517
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use it to keep track of the size of the `entries` array. An interim
solution until we have dynamic allocation.
Change-Id: Ib5f431bc0a72a79a53fa1376c3417942b19dd3a0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33516
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Process the "upper map" early as it doesn't depend on the descriptor
generation. This way, we can use it to guess the generation.
Change-Id: Ia2786b762ccefdce31b63397119bd89879e887ff
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Correct "firmware descriptor" to "flash descriptor". And also
move the check for peculiar descriptors and the message into an
inline function.
Change-Id: I7f15780e03d2fa17ca6d8328275cae5af13ae424
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55644
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When `CHIPSET_400_SERIES_COMET_POINT` got added, the `chipset_names`
table was not updated. Add the missing entry and reorder it to be
next to `CHIPSET_300_SERIES_CANNON_POINT` for consistency.
Change-Id: I4f4b31ecf91c432a2e82a92e274cb91ac166e635
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
The SPI hardware is pretty much unchanged from Apollo Lake. However, the
IFD differs significantly enough to require special handling.
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel C621A Lewisburg PCH belongs to C620 series, it has 0x34 as ICCRIBA.
Fix guess_ich_chipset_from_content() accordingly.
Print status info of read_ich_descriptors_from_dump() to facilitate
debugging upon failure.
TESTED=run flashrom successfully from OCP Yosemite V3 DeltaLake server.
Change-Id: I363aaccfb90e0a127c0f0bb0072e9e85c210b669
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/44621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The one in the `dummyflasher` is a little peculiar. We actually never
knew the type of the `st_size` field in `struct stat`. It happens to
be `signed` in some systems (e.g. DJGPP).
Change-Id: If36ba22606021400b385ea6083eacc7b360c20c5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Only minor differences in the Firmware Descriptor, compared to their
predecessors.
We extend our check on the `ICCRIBA` field in the descriptor to dis-
tinguish it from older generation. Alas, the `freq_read` field was
repurposed, so we can't use it as sanity check any more.
Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Mostly by changing to `unsigned` types where applicable, sometimes
`signed` types, and casting as a last resort.
Change-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
It's almost identical to 100 series PCHs and later. There are some
additional FREGs (12..15). To not clutter the `if` conditions further,
make more use of `switch` statements.
Tested on Kontron mAL10. Mark it as DEP as usually the last sector
is not covered by the descriptor layout and can't be read.
Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
None of these functions are used outside of the files they are defined
in, so make them all static.
Change-Id: Ie9cbe12d289bcedacf2f1bf483ae64ef8039ccc1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This should provide more flexibility while we don't have to allocate
256B extra per layout entry.
Change-Id: Ibb903113550ec13f43cbbd0a412c8f35fe1cf454
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
GCC is picky about the comment being where the break should go.
Change-Id: I05db2fb34025fefe2c6ddd1274c8e45b7cc5a4b6
Signed-off-by: Richard Hughes <richard@hughsie.com>
Reviewed-on: https://review.coreboot.org/c/30406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This adds PCI IDs for C620-series PCHs and adds
CHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum.
Lewisburg is very similar to Sunrise Point for Flashrom's purposes,
however one important difference is the way the "number of masters" is
interpreted from the flash descriptor (0-based vs. 1-based). There are
also new flash regions defined.
Change-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/20922
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Interpretation of component clocks changed. Also more regions and more
masters are supported now. The number of regions (NR) is now static per
chipset (10 in the 100 Series case) and not coded into the descriptor
any more.
v2: o Use guess_ich_chipset() for read_ich_descriptors_from_dump().
o Update region extraction in `ich_descriptors_tool`.
TEST=Run `ich_descriptors_tool` over a 100 Series dump and checked
that output looks sane. Run `ich_descriptors_tool` over dumps
of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge,
1 x Haswell). Beside whitespace changes, regions not accounted
by `NR` are not printed any more.
Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18973
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add guess_ich_chipset() that takes fields from a descriptor dump and
returns the lowest possible chipset version.
Intel did several incompatible changes to the descriptor through the
years. However, they forgot to add a version number. So we have to
apply some heuristics to detect the chipset version in case of exter-
nal flashing.
Change-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20246
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The condition `base > limit` is still valid since `base` is always at
least 4096 greater than `limit` in this case.
Change-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19046
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Sunrise Point PCH, paired with Skylake, has some minor changes
in the HW sequencing interface:
* Support for more flash regions moved PR* registers
* Only 4KiB erase blocks are supported by the primary erase command
* A second erase command for 64KiB pages was added
* More commands were added for status register access etc.
* A "Dedicated Lock Bits" register was added
No support for the new commands was added.
The SW sequencing interface seems to have moved register location and
is not supported any more officially. It's also untested.
Changes are loosely based on the Skylake support commit in Chromium OS
by Ramya Vijaykumar:
commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1
Author: Ramya Vijaykumar <ramya.vijaykumar@intel.com>
flashrom: Add Skylake platform support
Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Add a guard around read_ich_descriptors_via_fdo() which uses raw
hardware access and is only called from `ichspi`.
Fixes linking in case `NEED_RAW_ACCESS != 1`.
Change-Id: I5a35c607df44cdbcbacb960f8922c1bf9f1f2002
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20265
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The subtle difference was ignored when adding these chipsets. The
integrated Wildcat Point LP PCH is documented in [1].
I'm not sure how to account for "Broadwell H" which seems not publicly
documented. Maybe it's an unreleased HM9*, in which case the non-LP
path should be correct.
[1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O,
Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor
Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet
Revision 004
Document Number: 330837
Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18883
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+1 on everything doesn't make software greater per se.
v2: o Fix another +1.
o Amend style of similar (not +1 suffering) code, too.
Change-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add an option --ifd to read the ROM layout from an Intel Firmware
Descriptor (IFD). Works the same as the -l option, if given, -i
specifies the images to update.
v2: o Rebased on libflashrom, use libflashrom interface.
o Use functions from ich_descriptors.c.
v3: o Move ich_descriptors.o to LIB_OBJS, thus build it independent
of arch and programmers.
o Bail out if we aren't compiled for little endian.
o Update flashrom.8.tmpl.
v4: o Incorporated David's comments.
o Removed single-character `-d` option.
v5: Changed region names to match the output of `ifdtool --layout ...`
Change-Id: Ifafff2bf6d5c5e62283416b3269723f81fdc0fa3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I didn't really know what I was doing and hope removing the #ifdefs
doesn't have negative side effects.
The idea is to make the functions generally available for external
flashing (e.g. you might want to flash an Intel machine using an ARM
device as programmer).
Beware of big endian trouble, I guess. :-P
Change-Id: Ib3d38a622a581afee87b49777e775942cc901fc8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Silvermont (Bay Trail, Rangeley, Avoton) seems to still use the old
density encoding with 3 bits per chip. Documentation is unavailable
(held concealed by Intel) but thanks to the efforts of Tai-Hong
(Type) Wu the layout is clear now. This patch is based on his one
but solves the issue differently thus reducing the code complexity.
Corresponding to flashrom svn r1861.
Signed-off-by: Tai-Hong Wu <thwu@lunartoday.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
The Wildcat Point PCH can be paired with Broadwell or Haswell.
This patch was essentially backported from ChromiumOS commit 9bd2af8.
Corresponding to flashrom svn r1845.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
The core of this patch to support Bay Trail originally came from the
Chromiumos flashrom repo and was modified by Sage to support the
Rangeley/Avoton parts as well.
Because that was not complicated enough already Stefan Tauner refactored
and refined everything. Bay Trail seems to be the first Atom SoC able to
support hwseq. No SPI Programming Guide could be obtained so it is
handled similarly to Lynx Point which seems to be its nearest relative.
Corresponding to flashrom svn r1844.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Marc Jones <marcj303@gmail.com>
Tested-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Thomas Reardon <thomas_reardon@hotmail.com>
Tested-by: Wen Wang <wen.wang@adiengineering.com>
Acked-by: Marc Jones <marcj303@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Possible values as well as encodings have changed in newer chipsets as follows.
- Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all
operations
- Since Cougar Point the chipsets support dual output fast reads (encoded
in bit 30).
- Flash component density encoding has changed from 3 to 4 bits with Lynx
Point, currently allowing for up to 64 MB chips.
Corresponding to flashrom svn r1843.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Thanks to Idwer and clang for noticing these problems.
Corresponding to flashrom svn r1646.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
- allows for compilation with -Werror=shadow,
- use extended line limit to fix the most awful line breaks.
Corresponding to flashrom svn r1570.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This patch adds an external utility that shares most of the existing descriptor
decoding source code. Additionally to what is available via FDOC/FDOD this
allows to access:
- the softstraps which are used to configure the chipset by flash content
without the need for BIOS routines. on ICH8 it is possible to read those
with FDOC/FDOC too, but this was removed in later chipsets.
- the ME VSCC (Vendor Specific Component Capabilities) table. simply put,
this is an SPI chip database used to figure out the flash's capabilities.
- the MAC address stored in the GbE image.
Intel thinks this information should be confidential for ICH9 and up, but
references some tidbits in their public documentation.
This patch includes the human-readable information for ICH8, Ibex Peak
(5 series) and Cougar Point (6 series); the latter two were obtained from
leaked "SPI Flash Programming Guides" found by google. Data regarding ICH9
and 10 is unknown to us yet. It can probably found in:
"Intel® ICH7, ICH8, ICH9 and ICH10 — SPI Family Flash Programming Guide"
Information regarding the upcoming Panther Point chipset is also not included.
Corresponding to flashrom svn r1480.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Matthias Wenzel <bios@mazzoo.de>
This was done to ease the review. Another patch will hook up (and
explain) this code later.
Corresponding to flashrom svn r1452.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty
printing of those ICH/PCH flash descriptor sections that are
cached/mapped by the chipset (and which are therefore reachable via
FDOC/FDOD registers).
this includes the following:
- content section:
describes the image and some generic properties (number of
sections, offset of sections, PCH/ICH and MCH/PROC strap
offsets and lengths)
- component section:
identify the different SPI flash chips and their capabilities.
- region section
similarly to a partition table this describes the different regions.
the content of FLREG* is derived from this section.
- master section
defines SPI master (host, ME, GbE) access rights of the
individual regions. the content of PR* is derived from this section.
this is only a part of the data included in the descriptor. other
information can be retrieved from a complete binary dump of the
descriptor region only.
this patch also adds macros and pretty printing for "Vendor Specific
Component Capabilities" registers: there are two of them: lower and
upper. they describe the properties of the address space divided by
FPBA (which allows to use multiple flash chips or partitions with
different properties). the properties of all supported flash chips
(together with their RDIDs) are stored in the same format in table
in a descriptor section (which is used by the ME apparently). a
later patch will use the macros outside of ichspi.c which is the
reason why the prettyprinting function and the register bit macros
are not defined in ichspi.c but ich_descriptors.h (else they would
be moved in the follow-up patch).
because this patch relies on (compiler) implementation-specific
layouting of bit-fields, it checks for correct layout before taking
any action on runtime.
Corresponding to flashrom svn r1443.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
