The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the
Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted.
[1] Intel(R) 300 Series and Intel(R) C240 Series
Chipset Family Platform Controller Hub
Datasheet - Volume 1 of 2
Revison 4 (Dec 2018)
Document Number 337347
[2] Intel(R) 300 Series Chipset Families Platform Controller Hub
Datasheet - Volume 2 of 2
Revision 2? (Oct 2018)
Document Number 337348
Change-Id: If0b54799d5b93169ee660409bad57ae14677340c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jeremy Soller <jackpot51@gmail.com>
The MT25Q is the successor to the N25Q from Micron/Numonyx/ST. The MT25Q
is almost entirely backwards compatible with the N25Q series, however,
the MT25Q has additional subsector erase commands available, and there
are differences in stacked devices in the higher capacity variants. The
N25Q devices are left with "Micron/Numonyx/ST" as the vendor and MT25Q
devices are set with "Micron" as the vendor.
Signed-off-by: Jacob Creedon <jcreedon@google.com>
Change-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The AMD Am29F010 was marked TEST_OK_PRE in chromium repo change
SHA d217d1219ccaa43a01cd75475409183bd5714410. There are no other
differences in the definition of this chip.
This is the only change from the Chromium repo to be upstreamed for AMD
chips.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I7fa10d33b42c09d035c611535a54592083c4eaa0
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34534
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Intel 82802AB Was marked as TEST_OK_PREW in the Chromium fork in their
SHA312d9ff1fb1ccb5533a867d4248eb1be95ec3fbc. The definitions in the fork
and here in upstream are otherwise substantially similar.
There are no other downstream changes for Intel chips to be upstreamed.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Iec75f0b1c35000308601fa6fdd63ab1738d0ef94
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34533
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We never read the first 'ret'. Let's check the first 'ret'
and exit if it failed.
Also, print the version only when the command succeeded.
Found-by: scan-build 7.0.1-8
Change-Id: I4aac5e1f3bd0604b079e1fdd9b7f09f1f4fc2d7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34403
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It's almost identical to 100 series PCHs and later. There are some
additional FREGs (12..15). To not clutter the `if` conditions further,
make more use of `switch` statements.
Tested on Kontron mAL10. Mark it as DEP as usually the last sector
is not covered by the descriptor layout and can't be read.
Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For self-consistency, and to allow tools to assist with merging the
chromium fork of flashrom, sort the entries of flashchips.c. The file is
already largely sorted, though deviations have crept in over time.
This is a non-clever mostly ASCII-order sorting. It is not intended to
be permanent.
Change-Id: I75a99583592526f60ba5264e92391bf8b1213b20
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33931
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When trying to flash a single FMAP region on VBOOT enabled boards the
default of 32 entries is to small to store all regions. Flashrom will
bail out with "Cannot add fmap entries to layout - Too many entries."
Increase the maximum rom layout size to 128 to support complex FMAPs.
Tested on coreboot's UP/squared mainboard using SF600.
With this patch it's possible to update a single FMAP region.
Change-Id: I68084b08f7b35a162b5f2d3109d82a8b63c194ff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34025
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
To allow automated tools to manipulate flashchips.c, make the definition
of SFDP-capable chip more consistent with other definitions. This
involves
- reordering fields to match both other entries and the definition of
struct flashchip.
- reformatting comments to make them consistent with other entries.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I8708a11993822085b3e8d8c80532dfb935d39876
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The definition for the AT26DF321 has been commented out since it was
first added in 2008. The chip now appears to be obsolete, being marked
"obsolete" and unstocked at Digikey. It is also only referred to in
historical documents on the manufacturer's website (microchip.com).
To avoid further bitrot of this dead code, drop it.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ib30b3a16f25de5def508d90ec9375563b1d4d384
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
To allow automated tools to manipulate flashchips.c, ensure all
.block_erasers definitions have consistent formatting:
- start with the opening brace on a new line.
- ensure end brace indented exactly two tabs.
SFDP-capable chip is the one exception to this rule as it has an empty
block instead.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ib168bdbbef4cf097109805de15c97ecc1f7915b3
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33831
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To allow automated tools to manipulate flashchips.c, make end of line
comment formatting more consistent. Specifically, this change moves the
comma from end of line to immediately after the field value, before the
commment.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ic4f97454766eff640b26a6c6eca29dc56c34c444
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For consistency, and to make the file amenable to manipulation by tools,
use only tabs when indenting. Some previous changes had introduced
spaces for indenting.
Also ensure that every table entry is separated by a single blank line.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: Ib2193798cc52641d6c443f8851903c749b31cb74
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33828
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We are at version 1.1 now, and the user interface change in 0.9.6 was
to make setting the programmer mandatory. This was done all the way
back in 2012, so it is safe to remove these warnings now.
Change-Id: If1b379b7b8234d50a2f0a4f522f15820a1a6603c
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
These functions are no longer used, or were never used in the first place.
generate_testpattern() - Introduced in commit eaac68bf8b, never used
list_programmers() - Introduced in commit 552420b0d6, never used
pci_dev_find_filter() - Prototype removed in commit 5c316f9549
erase_chip_jedec() - Usage and prototype removed in commit f52f784bb3
printlock_regspace2_blocks() - Introduced in commit ef3ac8ac17, never used
spi_write_status_enable() - Usage dropped in commit fcbdbbc0d4
Change-Id: I742164670521fea65ffa3808446594848ce63cec
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We enforced a 16MiB limit in spi_read_chunked() for multi-die flash
chips that can't be fully read at once. The same limit can be useful
for dediprog programmers. So move it into a more generic place.
Change-Id: Iab1fd5b2ea550b4b3ef3e8402e0b6ca218485a51
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33613
Reviewed-by: Ryan O'Leary
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Asus set up HTTPS for their site, and redirects to that by default. So,
use this by default, which also saves one redirect.
```
$ curl -I http://www.asus.com/
HTTP/1.1 301 Moved Permanently
Content-Length: 0
Location: https://www.asus.com/
Date: Wed, 04 Oct 2017 11:15:14 GMT
Connection: keep-alive
X-Akamai-Device-Characteristics: desktop
X-Akamai-Device-Model: ; ; cURL; cURL
```
Use the command below to change the occurrences.
```
sed -i 's,http://www.asus.com,https://www.asus.com,g' print.c
```
Change-Id: I62319bfbf39c73f98ed3f865a11f4fe870befee4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/21874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
