This programmer operates much the same as realtek_mst_i2c_spi, so the
I2C options are moved to a new section describing both programmers
and a short description is added for this programmer itself.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I9ccb9694fdea29e68f062cc049efc0204917a139
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
This programmer was undocumented.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Idde5a8de014fe84c4a472f8fbfd3562350997d39
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
This change adds follow up changes to the man page:
- Explain (-) argument for -w/-v operations
- Expand on region name handling of -x operation
Also updates cli_classic.c to match with --help output.
BUG=b:224364316
Change-Id: I0cba593da3926c8587027789f4e1e89a2329ca7f
Signed-off-by: Daniel Campello <campello@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
It was absent from the list of emulated chips.
Change-Id: I50f6cd6c5d853d6c70921e8027ada52d27982708
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This section is rather outdated and should be dispensed with.
Change-Id: Id7e0ce412901ccb27124a9958d5ef214ab289518
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reintroduces a reworked version of the GPIOL pin control first
introduced in commit 3207844 (CB:49637), which was reverted in commit
6518cf3 (CB:55692) due to breakage.
This change introduces a new argument `gpiolX` to allow use of the four
GPIOL pins either as generic gpios or as additional CS# signal(s). `X`
specifies the GPIOL pin (0-3) to be set to one of [HLC] with the
following meaning:
* H - set the pin as output high
* L - set the pin as output low
* C - use the pin as additional CS# signal
The third value, `C`, aims to replace the parameter `csgpiol`, that is
now marked as deprecated and can be removed at some point in the future.
`gpiol` and `csgpiol` are mutually exclusive and use of both results in
an error.
Multiple pins may be set by specifying the parameter multiple times.
Documentation was updated/added accordingly.
Test: All pin levels/modes have been verified to behave correctly with a
logic analyzer.
Change-Id: I3989f0f9596c090de52dca67183b1363dae59d3a
Signed-off-by: Alan Green <avg@google.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/57810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Documentation for `csgpiol` was put into the generic programmer options
section. Move it to its own section.
Change-Id: Ic7379331d36b3068eacde5a983b4ccb3afc56c51
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/57893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The flashrom project no longer uses freenode. To avoid having outdated
man pages in the future, the contact methods are now listed in the wiki.
Change-Id: I75e8f43c50dc4c3feede0250334a877cdaac8103
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/56031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This change adds a 'psus=<on|off>' option, to control the external Vcc
state of the bus pirate, allowing hardware where the SPI flash chip is
powered by the 3V3/5V lines directly.
Change-Id: I8a7d4b40c0f7f04f6976f6757f05b61f2c9958f9
Signed-off-by: Jeremy Kerr <jk@codeconstruct.com.au>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is a follow up change of CB:52450
Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: Icc068f5545b6f30ac390b7b815a31e2d61bf4789
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Add an optional sub-parameter to the -i parameter to allow building the
image to be written from multiple files. This will also allow regions to
be read from flash and written to separate image files.
This is a rebase of a patch that was ported from chromiumos. A lot of
things have changed, but the idea is the same.
Original patch by Louis Yung-Chieh Lo <yjlou@chromium.org>:
Summary: Support -i partition:file feature for both read and write.
Commit: 9c7525f
Review URL: http://codereview.chromium.org/6611015
Ported version by Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
and Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>:
Summary: [PATCH 2/6] layout: Add -i <region>[:<file>] support.
Review URL: https://mail.coreboot.org/pipermail/flashrom/2013-October/011729.html
Change-Id: Ic5465659605d8431d931053967b40290195cfd99
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Signed-off-by: Daniel Campello <campello@chromium.org>
Co-Authored-by: Edward O'Callaghan <quasisec@google.com>
Co-Authored-by: Daniel Campello <campello@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/23021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This patch fixes a few bugs that two patches ( `3149822cd45cb2e5841e15d648783748ba1b2ec6` && `3b8fe0f8e907c0ba9f7c7935e950f3e1538d427f`) brought:
* Check the presence of 'size' param only if the emulate is VARIABLE_SIZE.
* Initialize 'flash->st->par.data' in dummy_init() so that it can probe the VARIABLE_SIZE emulator correct in probe_variable_size().
* Replace atoi() with strtol().
* Revise man page to describe how to use the VARIABLE_SIZE emulation target.
TEST:
$ flashrom -p dummy:image=dummy.bin,emulate=VARIABLE_SIZE,size=16777216 \
-w ${IMG} -V -f
...
Verifying flash... VERIFIED.
Writing dummy.bin
$ flashrom -p dummy:image=dummy.bin,emulate=VARIABLE_SIZE -w ${IMG} -V -f
...
dummy_init: the size parameter is not given.
Unhandled programmer parameters (possibly due to another failure): image=dummy.bin,
Error: Programmer initialization failed
$ flashrom -p dummy:image=dummy.bin,emulate=SST25VF040.REMS -c SST25LF040A -w ${IMG}
...
Erasing and writing flash chip... Erase/write done.
Verifying flash... VERIFIED.
$ man flashrom
...
* Dummy vendor VARIABLE_SIZE SPI flash chip (configurable size, page write)
Example: flashrom -p dummy:emulate=SST25VF040.REMS
To use VARIABLE_SIZE chip, size must be specified to configure the size of the flash chip as a power of two.
Example: flashrom -p dummy:emulate=VARIABLE_SIZE,size=16777216,image=dummy.bin
...
Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: Ie6481943a831b946a91b643b4d79e684c27e48b8
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This fixes a regression with the Fedora package.
Change-Id: I881bd5002a842072ce9dadea033c51a2668f9e7c
Signed-off-by: Richard Hughes <richard@hughsie.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38939
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Added spireadmode for >= Bolton.
Do not override speed or read mode for >= Bolton if parameter not
specified.
Minor cleanup of sb600spi.c code.
TEST=Manual: deploy on tremblye read flash using various parameters
BUG=b:147665085,b:147666328
BRANCH=master
Change-Id: Id7fec7eb87ff811148217dc56a86dca3fef122ff
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Tin Can Tools Flyswatter and Flyswatter 2 have a FT2232H
with a JTAG interface wired to port A. The buffers that drive the
JTAG pins need to be enabled with an nOE signal from the
FT2232H ADBUS6 and ADBUS7 pins.
Flyswatter has an ARM-14 JTAG interface and Flyswatter 2 has
an ARM-20 JTAG interface.
Change-Id: I56b1fb76dcda32bb02980cd54a2853506bfc9dfd
Signed-off-by: Russ Dill <Russ.Dill@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We have this in the ChromiumOS fork of flashrom which we rely
on to obtain the current flash chip in use. This ports it for
upstream consumption.
V.2: Constrain number_of_operations to one as per Nico's comment.
V.3: Rename '--get-size' to '--flash-size' however keep old arg as
'undocumented' for back-compat.
V.4: Add missing --help line.
V.5: Add man page entry.
V.6: Use printf() directly.
Change-Id: I8f002f3b2012aec4d26b0e81456697b9a5de28d6
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We have this in the ChromiumOS fork of flashrom which we rely
on to obtain the current flash chip in use. This ports it for
upstream consumption.
V.2: Constrain number_of_operations to one as per Nico's comment.
V.3: Move two goto's outside inner if-else block.
V.4: Add missing --help line.
V.5: Add man page entry.
v.6: Use printf() directly.
Change-Id: I23d574a2f8eaf809a5c0524490db9e3a560ede56
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We used to bail out on any unknown laptop. However, modern systems with
SPI flashes don't suffer from the original problem. Even if a flash chip
is shared with the EC, the latter has to expect the host to send regular
JEDEC SPI commands any time.
So instead of bailing out, we limit the set of buses to probe. If we
suspect to be running on a laptop, we only allow probing of SPI and
opaque programmers. The user can still use the existing force options
to probe all buses.
This will obsolete some board-enables that could be moved to `print.c`
in follow-up commits.
Change-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/28716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Flashmap, or simply fmap, is a binary data format for describing
region offsets, sizes, and certain attributes and is widely used by
coreboot. This patch adds support for the fmap data format version 1.1
and adds --fmap and --fmap-file arguments.
Using --fmap will make flashrom to search the ROM content for fmap
data. Using --fmap-file will make flashrom search a supplied file
for fmap data.
An example of how to update the COREBOOT region of a ROM:
flashrom -p programmer --fmap -w coreboot.rom -i COREBOOT
flashrom -p programmer --fmap-file coreboot.rom -w coreboot.rom -i COREBOOT
The fmap functions are mostly copied from cbfstool.
Currently it is made mutually exclusive with other layout options until
we are more clever about this input.
Change-Id: I0e7fad38ed79a84d41358e1f175c36d255786c12
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is driver that supports the Lattice iCE40 evaluation kits. On the
board is a SPI flash memory chip labeled ST 25P10VP.
Tested to work read/write/erase with "-p digilent_spi -c M25P10" or
with a patch that resets the part beforehands (in which case it gets
detected as a M25P10-A and is way faster due to paged writes).
Change-Id: I7ffcd9a2db4395816f0e8b6ce6c3b0d8e930c9e6
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/23338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Replace the `ich_spi_force` logic with more helpful warnings. These can
be hidden later, in case the necessary switches are detected. Also,
demote some warnings about settings that are the default nowadays (e.g.
SPI configuration lock, inaccessible ME region).
Change-Id: I94a5e7074b845c227e43d76d04dd1a71082a1cef
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This imports a series of patches from chromiumos for MTD support.
The patches are squashed to ease review and original Change-Ids have
been removed to avoid confusing Gerrit.
There are a few changes to integrate the code:
- Conflict resolution
- Makefile changes
- Remove file library usage from linux_mtd. We may revisit this and use
it for other Linux interfaces later on.
- Switch to using file stream functions for reads and writes.
This consolidated patch is
Signed-off-by: David Hendricks <dhendricks@fb.com>
The first commit's message is:
Initial MTD support
This adds MTD support to flashrom so that we can read, erase, and
write content on a NOR flash chip via MTD.
BUG=chrome-os-partner:40208
BRANCH=none
TEST=read, write, and erase works on Oak
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/272983
Reviewed-by: Shawn N <shawnn@chromium.org>
This is the 2nd commit message:
linux_mtd: Fix compilation errors
This fixes compilation errors from the initial import patch.
Signed-off-by: David Hendricks <dhendricks@fb.com>
This is the 3rd commit message:
linux_mtd: Suppress message if NOR device not found
This just suppresses a message that might cause confusion for
unsuspecting users.
BUG=none
BRANCH=none
TEST=ran on veyron_mickey, "NOR type device not found" message
no longer appears under normal circumstances.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302145
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This is the 4th commit message:
linux_mtd: Support for NO_ERASE type devices
Some mtd devices have the MTD_NO_ERASE flag set. This means
these devices don't require an erase to write and might not have
implemented an erase function. We should be conservative and skip
erasing altogether, falling back to performing writes over the whole
flash.
BUG=b:35104688
TESTED=Zaius flash is now written correctly for the 0xff regions.
Signed-off-by: William A. Kennington III <wak@google.com>
Reviewed-on: https://chromium-review.googlesource.com/472128
Commit-Ready: William Kennington <wak@google.com>
Tested-by: William Kennington <wak@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
This is the 5th commit message:
linux_mtd: do reads in eraseblock-sized chunks
It's probably not the best idea to try to do an 8MB read in one syscall.
Theoretically, this should work; but MTD just relies on the SPI driver
to deliver the whole read in one transfer, and many SPI drivers haven't
been tested well with large transfer sizes.
I'd consider this a workaround, but it's still good to have IMO.
BUG=chrome-os-partner:53215
TEST=boot kevin; `flashrom --read ...`
TEST=check for performance regression on oak
BRANCH=none
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344006
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This is the 6th commit message:
linux_mtd: make read/write loop chunks consistent, and documented
Theoretically, there should be no maximum size for the read() and
write() syscalls on an MTD (well, except for the size of the entire
device). But practical concerns (i.e., bugs) have meant we don't quite
do this.
For reads:
Bug https://b/35573113 shows that some SPI-based MTD drivers don't yet
handle very large transactions. So we artificially limit this to
block-sized chunks.
For writes:
It's not clear there is a hard limit. Some drivers will already split
large writes into smaller chunks automatically. Others don't do any
splitting. At any rate, using *small* chunks can actually be a problem
for some devices (b:35104688), as they get worse performance (doing an
internal read/modify/write). This could be fixed in other ways by
advertizing their true "write chunk size" to user space somehow, but
this isn't so easy.
As a simpler fix, we can just increase the loop increment to match the
read loop. Per David, the original implementation (looping over page
chunks) was just being paranoid.
So this patch:
* clarifies comments in linux_mtd_read(), to note that the chunking is
somewhat of a hack that ideally can be fixed (with bug reference)
* simplifies the linux_mtd_write() looping to match the structure in
linux_mtd_read(), including dropping several unnecessary seeks, and
correcting the error messages (they referred to "reads" and had the
wrong parameters)
* change linux_mtd_write() to align its chunks to eraseblocks, not page
sizes
Note that the "->page_size" parameter is still somewhat ill-defined, and
only set by the upper layers for "opaque" flash. And it's not actually
used in this driver now. If we could figure out what we really want to
use it for, then we could try to set it appropriately.
BRANCH=none
BUG=b:35104688
TEST=various flashrom tests on Kevin
TEST=Reading and writing to flash works on our zaius machines over mtd
Change-Id: I3d6bb282863a5cf69909e28a1fc752b35f1b9599
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/505409
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: William Kennington <wak@google.com>
Reviewed-on: https://review.coreboot.org/25706
Tested-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This patch sets the default baud rate for communication between
the host device and the Bus Pirate for hardware versions 3.0
and greater to 2M baud.
It also introduces the ability to manually set the baud rate via
the added 'serialspeed' programmer parameter.
This is done in two parts. Firstly, the requested serial speed is looked up
in a table to determine the appropriate clock divisor and the divisor is sent
to the bus pirate. Then, the system's baud rate for the selected serial port
is set using serial.c's 'serialport_config'. This function's prototype had to
be added to programmer.h.
In testing, using the 2M baud rate was able to significantly decrease
flash times (down from 20+ minutes to less than 2 minutes for an 8MB flash).
Change-Id: I3706f17a94fdf056063f2ad4a5f0a219665cdcbf
Signed-off-by: Shawn Anastasio <shawnanastasio@yahoo.com>
Reviewed-on: https://review.coreboot.org/23057
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an option --ifd to read the ROM layout from an Intel Firmware
Descriptor (IFD). Works the same as the -l option, if given, -i
specifies the images to update.
v2: o Rebased on libflashrom, use libflashrom interface.
o Use functions from ich_descriptors.c.
v3: o Move ich_descriptors.o to LIB_OBJS, thus build it independent
of arch and programmers.
o Bail out if we aren't compiled for little endian.
o Update flashrom.8.tmpl.
v4: o Incorporated David's comments.
o Removed single-character `-d` option.
v5: Changed region names to match the output of `ifdtool --layout ...`
Change-Id: Ifafff2bf6d5c5e62283416b3269723f81fdc0fa3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This option specifies to verify included regions only after a write.
It also reduces the data read before the write.
v2: o Changed short option name to `-N`.
o Added section in the manual page.
Change-Id: I40b5983f56d62821d17b827b88b73d1d41a30bd7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested mainboards:
OK:
- ASRock Fatal1ty 970 Performance and P4i65G
Reported by anonymous email message ID:
932677687262b1300eaf14260999d9262c31@guerrillamail.com
The latter actually had a tested board enable already.
Flash chips:
- Eon EN25Q128 to PREW (+PREW)
Reported by Adrian Graham
- GigaDevice GD25VQ41B to PREW (+PREW)
Reported by David Hendricks
- Winbond W39V040FB to PREW (+EW)
Reported by fjed on IRC
Miscellaneous:
- Change PCI IDs of "MS-6577 (Xenon)" board enable.
The previous IDs contained the on-board display adapter which is
disabled when a dedicated graphics card is installed.
- Add a note to the README how to overcome the clang warning if only a
single programmer is enabled.
- Fix some typo and manpage problems found by lintian
- r1920 introduced some explicit calls to pkg-config instead of $(PKG_CONFIG).
This patch corrects that.
- Make MS-7094 (K8T Neo2-F V2.0) board enable less contestable.
Previous PCI IDs were board-specific but ot the other of devices
that could be disabled by the firmware or that vary among
hardware revions. There are no good alternatives available.
However, since we always have a DMI decoder available now, we can
use non-board-specific devices without taking risks. Thanks to
Uwe Hermann for reporting and testing.
- Some other small changes to clean up whitespace and fix some warnings
from Debian's lintian.
Corresponding to flashrom svn r1951.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Apparently, there is at least one board of Russian origin (coined
SPI_TT LPT) that works with SPI Tiny Tools which is a closed-source
Windows GUI program somewhat similar to flashrom.
Corresponding to flashrom svn r1945.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This patch is based on Nico Huber's original version that was rebased
by David Hendricks for Chromium OS in
Change-Id: I84384b9d8ed53911657cf2293733531a6e11fd23
Corresponding to flashrom svn r1929.
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This patch has been cherry-picked from various patches in the chromiumos
tree denoted below.
Change-Id: I4b679e23ab37a4357b1e3d23f6f65a1c31f7d71a
Change-Id: Ibda56201ab4519315431c08206c61ceffb7c7e65
Change-Id: I540ad2d304dc69a7c79ca154beb744ef947ff808
Servo V2 has two FT4232H parts. The first one (denoted 'legacy') is
dedicated to supporting orginal Servo V1 functionality. The second,
residing at USB ID 0x18d1:5003 provides two other SPI interfaces on
port A and B respectively.
Additional changes by Alexandru Gagniuc, Hatim Kanchwala and Urja Rannikko:
- The clock divisor is set to '6', as this creates a 10MHz SPI clock,
which is the same SPI clock that the chromiumos branch produced.
- Add udev rule for Google servo boards to util/flashrom.rules.
- Add Google servo entry to manpage.
Corresponding to flashrom svn r1925.
Signed-off-by: Todd Broch <tbroch@chromium.org>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Hatim Kanchwala <hatim@hatimak.me>
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Hatim Kanchwala <hatim@hatimak.me>
Acked-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested mainboards:
OK:
- ASRock G31M-GS
Reported by Александр Трубицын
- ASRock G41M-VS3
Reported by Александр Трубицын
- ASRock N68C-S UCC
Reported by Alexey Belyaev
- ASRock AMCP7AION-HT (ION 330HT(-BD))
Reported by Stefan Tauner
- ASUS P5K SE
Reported by Александр Трубицын
- ASUS P5KPL-VM
Reported by Marin Vlah
- ASUS RAMPAGE III GENE
Reported by stevessss on IRC
- GIGABYTE GA-945GM-S2
Reported by Александр Трубицын
- GIGABYTE GA-945GCM-S2 (rev. 3.0)
Reported by Александр Трубицын
- GIGABYTE GA-965P-S3
Reported by Александр Трубицын
- GIGABYTE GA-EG43M-S2H
Reported by Александр Трубицын
- GIGABYTE GA-EP31-DS3L (rev. 1.0)
Reported by Александр Трубицын
- GIGABYTE GA-G33M-S2
Reported by Александр Трубицын
- GIGABYTE GA-G33M-S2L
Reported by Александр Трубицын
- GIGABYTE GA-H55M-S2
Reported by Александр Трубицын
- GIGABYTE GA-J1900N-D3V
Reported by Marcos Truchado and Guillermo von Hünefeld
- GIGABYTE GA-K8NS
Reported by nicolae788
- GIGABYTE GA-M56S-S3
Reported by Estevo Paz Freire
- GIGABYTE GA-P31-DS3L
Reported by Александр Трубицын
- GIGABYTE GA-P31-S3G
Reported by Александр Трубицын
- MSI MS-7336
Reported by Benjamin Bellec
- MSI X79A-GD45 (8D) (MS-7760)"
Reported by mortehu on IRC
- Supermicro A1SAi-2550F
Reported by Bernard Grymonpon
- Supermicro X7DWT
Reported by Steven Stremciuc
Laptop:
- ASUS U38N
Reported by Ultra on IRC
- Dell Latitude D630
Reported by Márton Miklós
- Fujitsu Amilo Xi 3650
Reported by Elmar Stellnberger
- Lenovo T400 (whitelisting only)
Chipsets:
- Mark 8086:1f38 (Intel Avoton/Rangeley) as tested
Reported by Jeremy Porter and Bernard Grymonpon
- Add Intel Sunrise Point IDs but no support yet.
Flash chips:
- Atmel AT45DB321D to PREW (+PREW)
Reported by The Raven
- Eon EN25QH32 to PREW (+PREW)
Reported by Josua Mayer
- Eon EN25QH64 to PREW (+EW)
Reported by David s. Alessio
- GigaDevice GD25LQ64(B) to PREW (+PREW)
Reported by Greg Tippit
- Intel 28F001BN/BX-T to PREW (+EW)
Reported by Lu Xie
- Micron M25P10-A to PREW (+W)
Reported by the Raven
- Micron M25PE40
Reported by David Wood
- Micron N25Q128..3E to PREW (+PREW)
Reported by Miklós Márton
- Macronix MX25L3273E to PREW (+PREW)
Reported by Roklobsta on IRC
- Macronix MX23L6454 to PR (+PR)
Reported by Steven Honeyman
- Macronix MX25U6435E/F to PREW (+PREW)
Reported by Marcos Truchado and Guillermo von Hünefeld
- PMC Pm25LQ032C to PREW (+EW)
Reported by Dirk Knop
- Spansion S25FL016A to PREW (+EW)
Reported by Márton Miklós
- Spansion S25FL128S......0 to PREW (+PREW)
Reported by Jim Houston
- Spansion S25FL204K to PR (+PR)
Reported by Thomas Debrunner
- SST SST49LF016C to PREW (+EW)
Reported by Steven Stremciuc
- SST SST39VF040 to PREW (+PREW)
Reported by Xavier Bourgeois
- SST SST49LF040B to PREW (+EW)
Reported by Rikard Åhlund
- ST M25P10-A to PREW (+W)
Reported by Martijn Schiedon
- Winbond W39V040FA to PREW (+EW)
Reported by Евгений Черкашин
- Winbond W39V080FA to PREW (+EW)
Reported by protagonist0 on IRC
- Winbond W25Q80.W to PREW (+PREW)
Reported by Miklós Márton
- Winbond W25X64 to PREW (+REW)
Reported by Johannes Krampf and Manuel Dejonghe
- Fix ID of AMIC A25LQ64
Reported by Roman Titov
- Fix page size of Spansion S25FL129P......1
Copy and paste error from the 128S uniform 256kB variant, probably.
- Add Micron/Numonyx phase-change memory IDs
Miscellaneous:
- Detect Android target OS.
No changes are required to build flashrom (excluding programmers
with NEED_PCI) on Android.
- Update rayerspi (spipgm) URL
- Fix max_data_write handling of at45db.
- Minor refinement of the README
- Mark board enable for the GA-K8NS variants as tested.
Tested by "nicolae788" on a board with socket 754.
- Mark "Multi-system" chassis as non-laptop case.
- Remove W836xx log requests.
We got enough (and no one is looking at them for the time being anyway).
- serprog: improve invalid reply error message, contributed by Urja Rannikko.
- Remove default include paths for MinGW.
- Disable implicit rules in the Makefile because we don't need them and they
just make the build (imperceptibly) slower.
- Enable our own strnlen() implementation not only on DJGPP but also if
HAVE_STRNLEN is not defined. This is needed to get older BSDs
(e.g. NetBSD 6.0, FreeBSD < 8.0) to work.
- Tiny other stuff.
Corresponding to flashrom svn r1917.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Supported controllers are Promise PDC20262 (FastTrak66/Ultra66),
PDC20265 (FastTrak100 Lite/Ultra100), PDC20267 (FastTrak100/Ultra100).
At least the Ultra100 only has address lines A0-A14 wired up, limiting
addressable chip size to 32 kB. The flash chips mounted on those
controllers usually is 128 kB, i.e. parts of the flash chip are
inaccessible. As a workaround, the driver implicitly truncates the
size of all flash chips to 32 kB. Works well for the factory installed
flash.
Do NOT use as a generic programmer for chips >32 kB.
Corresponding to flashrom svn r1916.
Signed-off-by: Joseph C. Lehner <joseph.c.lehner@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Urja Rannikko <urjaman@gmail.com>
Also, add a target to the makefile to build a flashrom.8.html with groff.
To fix some formatting issues this adds some indention commands as well.
Corresponding to flashrom svn r1913.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
On USB-based serial connections (VCP) the requested baud rate usually
does not matter (much). Remove the arbitrary restriction and use whatever
default values the OS/hardware provides.
Corresponding to flashrom svn r1907.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Urja Rannikko <urjaman@gmail.com>
This patch was inspired by the code in AVRDude (open source Atmel AVR
programmer) to support the PICkit2 written by Doug Brown [1]. The
Dediprog code in flashrom was used as the template for this code with
some reference to the ft2232 code as well.
[1] - https://github.com/steve-m/avrdude/blob/master/pickit2.c
Corresponding to flashrom svn r1881.
Signed-off-by: Justin Chevrier <jchevrier@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested mainboards:
OK:
- AOpen UK79G-1394 (used in EZ18 barebones)
Reported by Lawrence Gough
- ASUS M4N78 SE
Reported by Dima Veselov
- ASUS P5LD2-VM
Mark board enable as tested (reported by Dima Veselov)
- GIGABYTE GA-970A-UD3P (rev. 2.0)
Reported by trucmar on IRC
- GIGABYTE GA-990FXA-UD3 (rev. 4.0)
Reported by ROKO__ on IRC
- GIGABYTE GA-H77-DS3H (rev. 1.1)
Reported by Evgeniy Edigarev
- GIGABYTE GA-P55-USB3 (rev. 2.0)
Reported by Måns Thörnqvist
- MSI MS-7817 (H81M-E33)
Reported by Igor Kolker
Chipsets:
- Marked Intel Bay Trail (0x0f1c) as tested OK
Reported by Antonio Ospite
- Refine Intel IDs
* Add IDs for Braswell
* Add IDs for 9 Series PCHs (e.g. H97, Z97)
* Rename Wellsburg devices slightly
Flash chips:
- Atmel AT25DF041A to PREW (+PREW)
Reported by Tai-hwa Liang
- Atmel AT26DF161 to PREW (+EW)
Reported by Steve Shenton
- Atmel AT45DB011D to PREW (+PREW)
Reported by The Raven
- Atmel AT45DB642D to PREW (+PREW)
Reported by Mahesh Mokal
- Eon EN25F32 to PREW (+PREW)
Reported by Arman Khodabande
- Eon EN25F40 to PREW (+REW)
Reported by Jerrad Pierce
- Eon EN25QH16 to PREW (+EW)
Reported by Ben Johnson
- GigaDevice GD25Q20(B) to PREW (+PREW)
Reported by Gilles Aurejac
- Macronix MX25U6435E/F to PR (+PR)
Reported by Matt Taggart
- PMC Pm25LV512(A) to PREW (+PREW)
Reported by The Raven
- SST SST39VF020 to PREW (+PREW)
Reported by Urja Rannikko
- Winbond W25Q40.V to PREW (+EW)
Reported by Torben Nielsen
- Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E).
- Add MX25L6465E variant.
- There was never a MX25L12805 AFAICT.
- Split MX25L12805 from models with the same ID but an additional 32 kB
eraser: MX25L12835F/MX25L12845E/MX25L12865E.
- Add a bunch of ST parallel NOR flash chip IDs.
Miscellaneous:
- Whitelist ThinkPad X200.
- Constify master parameter of register_master().
- Remove FEATURE_BYTEWRITES because it was never used at all.
- Refine hwseq messages and make them less prominent.
- Fix the yet unused PRIxCHIPADDR format string thingy.
- Fix copy&paste error in spi_prettyprint_status_register_bp().
Spotted by Pablo Cases.
- Add an additional SMBus controller revision to identify another Yangtze
model. Thanks to Dan Christensen for reporting this issue.
- dediprog: add missing include for stdlib.h.
This fixes (at least) building on FreeBSD and DragonflyBSD with gcc.
- Remove references to struct pci_filter from programmer.h.
It is only needed in internal.c where it has a complete type. Having
it in programmer.h provokes a warning by some old versions of gcc.
- Tiny other stuff.
Corresponding to flashrom svn r1879.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Basically, among other chips, MSTAR manufactures SoCs that equip TV sets
and computer screens, and it seems that all of their products use the
same in-system programming protocol. Basically, they use the DDC channel
of VGA or DVI connectors, which is actually an I2C bus, to encapsulate
SPI frames (the flash chip is connected to the SoC through an SPI bus).
I wrote this patch since the screen I bought had a software bug, and the
manufacturer only released a new firmware binary, but no tool or
instructions on flashing it.
More details can be found here:
http://boeglin.org/blog/index.php?entry=Flashing-a-BenQ-Z-series-for-free(dom)
I only read code from Linux kernel archives published by Acer to figure
out the protocol (for a touchscreen controller and an NFC chip, both by
MSTAR, that share the same ISP protocol), so I don't think there are
any legal problems with it.
Compilation is currently disabled by default in the Makefile.
If in doubt, additional Makefile bugs were added by Stefan.
Corresponding to flashrom svn r1860.
Signed-off-by: Alexandre Boeglin <alex@boeglin.org>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested mainboards:
OK:
- ASUS F2A85-M
Reported by various corebooters
- ASUS M2N-MX SE Plus
Reported by Antonio
- ASUS P5LD2
Reported by François Revol
- Lenovo ThinkPad T530
Reported and partially authored by Edward O'Callaghan
- MSI MS-7502 (Medion MD8833)
Reported by naq on IRC
- Shuttle AB61
Reported by olofolleola4
- ZOTAC IONITX-F-E
Reported by Bernardo Kuri
Flash chips:
- Atmel AT45DB021D to PREW (+PREW)
Reported by The Raven
- Atmel AT25F4096 to PREW (+PREW)
Reported by 공준혁
- GigaDevice GD25Q16(B) to PREW (+PREW)
Reported by luxflow@live.com using a GD25Q16BSIG
- Catalyst CAT28F512
Mark erase and write as known bad (not implemented)
Miscellaneous:
- Various spelling corrections by Daniele Forsi.
- Added and refined a bunch of chips originally investigated by Carl-Daniel.
- Marked the ARM-USB-OCD-H programmer as tested
(reported by Ruud Schramp).
- Tiny other stuff.
Corresponding to flashrom svn r1839.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This patch lets you read and write the EEPROM on 82580-based gigabit NIC
cards. So far it has been tested on copper NICs only, but other variants
employing this controller should work too.
It is a nice substitution for the official eeupdate tool.
Speed is quite decent: less than 4 seconds for erases or writes of 32 kB.
Corresponding to flashrom svn r1832.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This PCI PATA controller can use 3V parallel flash up to 128 kB.
My card was identified as:
PCI 1283:8212, subsystem 1283:0001.
and labelled as:
Innovision Multimedia LTD.
EIO ATA133 RAID
(DM-8401 Ver A)
This particular card did not require setting of any GPIO signals to
enable flash writing. My card has Pm39LV512 in PLCC32 package without
socket.
Rebased by Stefan (automatic cleanup, some PCI changes, changed
enable bit handling). Committed with test state NT because the
rebased version was not tested on real hardware (yet).
Corresponding to flashrom svn r1812.
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Corresponding to flashrom svn r1811.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
