Tested on Bifferboard.
Corresponding to flashrom svn r1489.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
All programmers are now calling programmer registration functions and
direct manipulations of buses_supported are not needed/possible anymore.
Note: Programmers without parallel/LPC/FWH chip support should not call
register_par_programmer().
Additional fixes:
Set max_rom_decode.parallel for drkaiser.
Remove abuse of programmer_map_flash_region in it85spi.
Annotate several FIXMEs in it85spi.
Corresponding to flashrom svn r1463.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Based on the new opaque programmer framework this patch adds support
for Intel Hardware Sequencing on ICH8 and its successors.
By default (or when setting the ich_spi_mode option to auto)
the module tries to use swseq and only activates hwseq if need be:
- if important opcodes are inaccessible due to lockdown
- if more than one flash chip is attached.
The other options (swseq, hwseq) select the respective mode (if possible).
A general description of Hardware Sequencing can be found in this blog entry:
http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/
Besides adding hwseq this patch also introduces these unrelated changes:
- Fix enable_flash_ich_dc_spi to pass ERROR_FATAL from ich_init_spi.
The whole error handling looks a bit odd to me, so this patch does
change very little. Also, it does not touch the tunnelcreek method,
which should be refactored anyway.
- Add null-pointer guards to find_opcode and find_preop
to matches the other opcode methods better:
curopcodes == NULL has some meaning and is actively used/checked in
other functions.
TODO: adding real documentation when we have a directory for it
Corresponding to flashrom svn r1461.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The type member is enough most of the time to derive the wanted
information, but
- not always (e.g. ich_set_bbar),
- only available after registration, which we want to delay till the
end of init, and
- we really want to distinguish between chipset version-grained
attributes which are not reflected by the registered programmer.
Hence this patch introduces a new static variable which is set up
early by the init functions and allows us to get rid of all "switch
(spi_programmer->type)" in ichspi.c. We reuse the enum introduced
for descriptor mode for the type of the new variable.
Previously magic numbers were passed by chipset_enable wrappers. Now
they use the enumeration items too. To get this working the enum
definition had to be moved to programmer.h.
Another noteworthy detail: previously we have checked for a valid
programmer/ich generation all over the place. I have removed those
checks and added one single check in the init method. Calling any
function of a programmer without executing the init method first, is
undefined behavior.
Corresponding to flashrom svn r1460.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
- introduce a new variable 'wanted' that is used instead of 'new'
- use 'new' for the actual value contained in BIOS_CNTL after we tried to write it
- rephrase the warning which now also includes the old and new values besides the wanted one
Corresponding to flashrom svn r1435.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Intel's Tunnel Creek chipset supports both an SPI and an LPC bus. Set the
chipset table entry for Tunnel Creek to the new function
enable_flash_tunnelcreek(), which will read the hardware straps and return
support for the bus that has been used for booting. This function uses
ich_init_spi() with ich_generation set to 7 for initializing the SPI bus
if necessary.
SPI functionality tested on actual hardware, Tunnel Creek LPC interface not
tested yet (missing hardware for that).
Log file / success report:
http://www.flashrom.org/pipermail/flashrom/2011-September/007823.html
Corresponding to flashrom svn r1430.
Signed-off-by: Ingo Feldschmid <ifel@msc-ge.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
The meaning of the bits involved has changed several times in the past.
This patch takes these changes into account and hence fixes the output of the
pretty printing of GCS on all SPI-supported Intel chipsets that are not ICH7 or
NM10 (the latter were unaffected, because the defaults were correct).
This patch also allows to differentiate Ibex Peak and Cougar Point chipsets from
the earlier chipset series (ICH10) by adding new wrapper functions that set
"ich_generation" to 11 and 12 respectively. This should not change behavior
outside of enable_flash_ich_dc_spi, because the code path for
ich_generation >=9 is equal.
alternatively we could just remove the pretty printing of GCS and just output
the bits involved. i would like to keep the pch differentiation anyway though,
because i feel it will become handy in the future.
tested on my QS57-based thinkpad (probe + partial read)
Corresponding to flashrom svn r1423.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
AMD Hudson has different vendor/device IDs than AMD SBx00, handle
that properly.
Corresponding to flashrom svn r1422.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
- Mixing uninitialized and initialized local variables leads to
confusion.
- ft2232_spi error cases should have gotten some error handling, and
that's the reason the curly braces were there.
- Fixing typos/wording in some places would have been nice given that
those places were touched anyway.
Corresponding to flashrom svn r1413.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
It is based on Joshua Roys' RE.
http://www.flashrom.org/pipermail/flashrom/2011-August/007504.html
Corresponding to flashrom svn r1408.
Tested-by: Márton Miklós
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
The OEM BIOS on the EPoX EP-8PA7I and a number of other boards clear
byte 0x92 in the LPC bridge configuration space. Do the same for
all CK804 chips, assuming this to be some sort of chipset-generic
write-enable.
Currently the same chipset enable is used for MCP51 (nForce 430).
There have been reports of successful writes with its variations
(e.g. A8N-LA (Nagami-GL8E)), but they were not tagged as OK. Due to
the new "unsupported chipset"-message we will get success reports in
the case this patch does not break anything on the MCP51-based boards.
See also:
http://www.flashrom.org/pipermail/flashrom/2011-July/007252.htmlhttp://patchwork.coreboot.org/patch/3176/
Corresponding to flashrom svn r1405.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Joshua Roys <roysjosh@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Corresponding to flashrom svn r1403.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Also, indentation fixes, e.g. due to conversion to msg_*, use ARRAY_SIZE
where possible, wrap overly long line, etc.
Compile-tested. There should be no functional changes.
Corresponding to flashrom svn r1397.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
It's shorter to type, and we have less problems with the 80 column limit.
Corresponding to flashrom svn r1396.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
The code took 32 bits of input and wrote them to an 48 bit register,
duplicating some values.
Document the fwh_idsel= parameter in the man page.
Corresponding to flashrom svn r1389.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Old output:
Calibrating delay loop... OK.
Found chipset "Intel QS57", enabling flash write... OK.
This chipset supports the following protocols: FWH, SPI.
new non-verbose output for tested chipsets:
Calibrating delay loop... OK.
Found chipset "Intel QS57". Enabling flash write... OK.
This chipset supports the following protocols: FWH, SPI.
new non-verbose output for untested chipsets:
Found chipset "Intel QS57".
This chipset is marked as untested. If you are using an up-to-date version
of flashrom please email a report to flashrom@flashrom.org including a
verbose (-V) log.
Enabling flash write... OK.
This chipset supports the following protocols: FWH, SPI.
Corresponding to flashrom svn r1379.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This was deliberately disabled until now, but seems to work well enough.
Corresponding to flashrom svn r1372.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
As defined by Intel 6 Series Chipset and Intel C200 Series Chipset
Specification Update; document number 324646-006, May 2011.
Corresponding to flashrom svn r1344.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This patch combines three previously posted patches in a revised form.
one is even stolen from Stefan Reinauer (remove umlauts from man page).
Corresponding to flashrom svn r1317.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Corresponding to flashrom svn r1295.
Signed-off-by: John Schmerge <jbschmerge@gmail.com> for Devon IT
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This patch fixes the "using plain integer as NULL pointer" warnings
generated by running sparse on the flashrom source.
Corresponding to flashrom svn r1255.
Signed-off-by: Peter Huewe <peterhuewe@gmx.de>
Acked-by: Mathias Krause <mathias.krause@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
The address part was using a bit of the size, the size was missing the
upper bit, was off by 1023 bytes and included the protection bits.
Corresponding to flashrom svn r1250.
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This means all chipset enables etc. will be undone on shutdown.
Reversible PCI config space writes now use rpci_write_*().
PCI config space writes which are one-shot (e.g. communication via
config space) should continue to use the permanent pci_write_*
variants.
Extend the number of available register_shutdown slots to 32.
Corresponding to flashrom svn r1232.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
A lot of messages sent@flashrom.org just have "flashrom -V" as the subject.
Ask people to include more information in the subject line to make life
easier for developers/supporters.
Corresponding to flashrom svn r1202.
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This also adds (and marks as tested) a chipset-enable for the SiS 741.
All operations successfully tested on hardware.
lspci/superiotool:
http://www.flashrom.org/pipermail/flashrom/2010-September/004710.html
Corresponding to flashrom svn r1192.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
SiS 745 chipset + Winbond W83697HF and Winbond W49F002U flash. Probe, read,
erase and write all work.
Matching on "NB/SB" (they are integrated). Also mark SiS 745 chipset
as tested.
lspci/superiotool:
http://www.flashrom.org/pipermail/flashrom/2010-September/004705.html
Corresponding to flashrom svn r1158.
Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
(At least) for the QM57 which i have tested an additional patch was
needed as some reserved bits in the "Software Sequencing Flash Control
Register" (SSFC) needs to be programmed to 1 in the QM57.
Corresponding to flashrom svn r1137.
Signed-off-by: Helge Wagner <helge.wagner@ge.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
- Fix incorrect whitespace, indentation, and coding style in some places.
- Drop '/**' Doxygen comments, we don't use Doxygen. Even if we would use
it, the comments are useless as we don't have any Doxygen markup in there.
- Use consistent vendor name spelling as per current website (NVIDIA,
abit, GIGABYTE).
- Use consistent / common format for "Suited for:" lines in board_enable.c.
- Add some missing 'void's in functions taking no arguments.
- Add missing fullstops in sentences, remove them from non-sentences (lists).
Corresponding to flashrom svn r1134.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Tested on Asus P4S800-MX.
Corresponding to flashrom svn r1128.
Signed-off-by: David Borg <borg.db@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Huge thanks go to Michael Karcher for reverse engineering the interface
and to Johannes Sjölund for testing the first iterations of my patch on
his hardware until it worked.
Thanks to the following testers of the patch:
* MCP61, 10de:03e0, LPC OK, ECS Geforce6100SM-M, Andrew Cleveland
* MCP61, 10de:03e0, LPC OK, Biostar NF520-A2 NF61D-A2, Vitaliy Buchynskyy
* MCP65, 10de:0441, SPI OK, MSI MS-7369 K9N Neo-F v2, Kjell Braden
* MCP65, 10de:0441, SPI OK, MSI MS-7369, Wolfgang Schnitker
* MCP65, 10de:0441, SPI OK, MSI MS-7369, Johannes Sjölund
* MCP65, 10de:0441, SPI OK, MSI MS-7369, Melchior Franz
* MCP78S, 10de:075c, SPI OK, Asus M3N78 PRO, Brad Rogers
* MCP78S, 10de:075c, SPI OK, Asus M3N78-VM, Marcel Partap
* MCP78S, 10de:075c, SPI OK, Asus M4N78 PRO, Kimmo Vuorinen
* MCP78S, 10de:075c, SPI OK, Asus M4N78 PRO, Vikram Ambrose
* MCP79, 10de:0aad, SPI OK, Acer Aspire R3600, Andrew Morgan
* MCP79, 10de:0aae, LPC ??, Lenovo Ideapad S12 laptop, Christian Schmitt
* MCP79, 10de:0aae, SPI OK, Apple iMac9,1 Mac-F2218EA9, David "dledson"
flashrom will refuse to write/erase for safety reasons if MCP6x/MCP7x
SPI is detected.
Corresponding to flashrom svn r1113.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Programmer specific functions are of absolutely no interest to any file
except those dealing with programmer specific actions (special SPI
commands and the generic core).
The new header structure is as follows (and yes, improvements are
possible):
flashchips.h flash chip IDs
chipdrivers.h chip-specific read/write/... functions
flash.h common header for all stuff that doesn't fit elsewhere
hwaccess.h hardware access functions
programmer.h programmer specific functions
coreboot_tables.h header from coreboot, internal programmer only
spi.h SPI command definitions
Corresponding to flashrom svn r1112.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Convert all PCI-based external programmers to use special little-endian
accessors for all MMIO regions of PCI devices. This patch does _not_
touch the internal programmer (which is PCI-based as well).
Huge thanks go to Misha Manulis who worked with me to create a first
version of this patch for the satasii programmer based on modification
of generic code.
Huge thanks also go to Segher Boessenkool for suggesting the pci_mmio_
prefix for the abstraction layer.
NOTE to package maintainers: With this patch, compilation and usage of
flashrom should be safe on x86, x86_64, MIPS (little and big endian) and
PowerPC (big endian).
The internal programmer is disabled on non-x86/x86_64 (but it
compiles). The atahpt, nic3com, nicnatsemi, nicrealtek and rayer_spi
can not be compiled on non-x86/x86_64 because port space I/O is
not (yet) supported. Please compile with default settings on
x86/x86_64 and with the following settings on all other architectures:
make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no CONFIG_NICNATSEMI=no
CONFIG_RAYER_SPI=no
Corresponding to flashrom svn r1111.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Misha Manulis <misha@manulis.com>
Smarter version could decide whether SPI is vital or not depending on
straps. Straps are currently implemented for ICH7. EP80579 is in the comment,
PCH of 5 Series/3400 Series has "LPC, reserved, PCI, SPI".
Corresponding to flashrom svn r1098.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>