mirror of
https://review.coreboot.org/flashrom.git
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Right now, the annotation only differentiates between SPI and non-SPI. Anyone who knows more about a specific flash chip should feel free to update it. The existing flashbus variable was abused to denote the SPI controller type. Use an aptly named variable for that purpose. Once this patch is merged, the chipset/programmer init functions can set supported flash chip types and flashrom can automatically select only matching probe/read/erase/write functions. A side benefit of that will be the elimination of the Winbond W29EE011 vs. AMIC A49LF040A conflict. Corresponding to flashrom svn r556. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
176 lines
4.7 KiB
C
176 lines
4.7 KiB
C
/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2008 Wang Qingpei <Qingpei.Wang@amd.com>
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* Copyright (C) 2008 Joe Bao <Zheng.Bao@amd.com>
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <string.h>
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#include <sys/mman.h>
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#include "flash.h"
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#include "spi.h"
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struct sb600_spi_controller {
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unsigned int spi_cntrl0; /* 00h */
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unsigned int restrictedcmd1; /* 04h */
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unsigned int restrictedcmd2; /* 08h */
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unsigned int spi_cntrl1; /* 0ch */
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unsigned int spi_cmdvalue0; /* 10h */
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unsigned int spi_cmdvalue1; /* 14h */
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unsigned int spi_cmdvalue2; /* 18h */
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unsigned int spi_fakeid; /* 1Ch */
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};
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struct sb600_spi_controller *spi_bar = NULL;
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uint8_t *sb600_spibar;
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int sb600_spi_read(struct flashchip *flash, uint8_t *buf)
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{
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int rc = 0, i;
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int total_size = flash->total_size * 1024;
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int page_size = 8;
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for (i = 0; i < total_size / page_size; i++)
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spi_nbyte_read(i * page_size, (void *)(buf + i * page_size),
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page_size);
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return rc;
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}
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uint8_t sb600_read_status_register(void)
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{
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const unsigned char cmd[0x02] = { JEDEC_RDSR, 0x00 };
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unsigned char readarr[JEDEC_RDSR_INSIZE];
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/* Read Status Register */
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spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
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return readarr[0];
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}
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int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf)
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{
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int rc = 0, i;
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int total_size = flash->total_size * 1024;
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int result;
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/* Erase first */
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printf("Erasing flash before programming... ");
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flash->erase(flash);
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printf("done.\n");
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printf("Programming flash");
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for (i = 0; i < total_size; i++, buf++) {
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spi_disable_blockprotect();
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result = spi_write_enable();
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if (result)
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return result;
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spi_byte_program(i, *buf);
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/* wait program complete. */
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if (i % 0x8000 == 0)
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printf(".");
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while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
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;
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}
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printf(" done.\n");
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return rc;
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}
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void reset_internal_fifo_pointer(void)
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{
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mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2);
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while (mmio_readb(sb600_spibar + 0xD) & 0x7)
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printf("reset\n");
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}
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void execute_command(void)
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{
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mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2);
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while (mmio_readb(sb600_spibar + 2) & 1)
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;
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}
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int sb600_spi_command(unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr, unsigned char *readarr)
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{
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int count;
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/* First byte is cmd which can not being sent through FIFO. */
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unsigned char cmd = *writearr++;
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writecnt--;
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spi_bar = (struct sb600_spi_controller *) sb600_spibar;
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printf_debug("%s, cmd=%x, writecnt=%x, readcnt=%x\n",
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__func__, cmd, writecnt, readcnt);
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if (readcnt > 8) {
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printf("%s, SB600 SPI controller can not receive %d bytes, "
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"which is limited with 8 bytes\n", __func__, readcnt);
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return 1;
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}
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if (writecnt > 8) {
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printf("%s, SB600 SPI controller can not sent %d bytes, "
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"which is limited with 8 bytes\n", __func__, writecnt);
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return 1;
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}
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mmio_writeb(cmd, sb600_spibar + 0);
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mmio_writeb(readcnt << 4 | (writecnt), sb600_spibar + 1);
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/* Before we use the FIFO, reset it first. */
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reset_internal_fifo_pointer();
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/* Send the write byte to FIFO. */
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for (count = 0; count < writecnt; count++, writearr++) {
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printf_debug(" [%x]", *writearr);
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mmio_writeb(*writearr, sb600_spibar + 0xC);
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}
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printf_debug("\n");
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/*
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* We should send the data by sequence, which means we need to reset
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* the FIFO pointer to the first byte we want to send.
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*/
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reset_internal_fifo_pointer();
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execute_command();
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/*
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* After the command executed, we should find out the index of the
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* received byte. Here we just reset the FIFO pointer, skip the
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* writecnt, is there anyone who have anther method to replace it?
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*/
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reset_internal_fifo_pointer();
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for (count = 0; count < writecnt; count++) {
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cmd = mmio_readb(sb600_spibar + 0xC); /* Skip the byte we send. */
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printf_debug("[ %2x]", cmd);
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}
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printf_debug("The FIFO pointer 6 is %d.\n", mmio_readb(sb600_spibar + 0xd) & 0x07);
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for (count = 0; count < readcnt; count++, readarr++) {
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*readarr = mmio_readb(sb600_spibar + 0xC);
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printf_debug("[%02x]", *readarr);
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}
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printf_debug("\n");
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return 0;
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}
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