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Add bus type annotation to struct flashchips

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Right now, the annotation only differentiates between SPI and non-SPI.
Anyone who knows more about a specific flash chip should feel free to
update it.

The existing flashbus variable was abused to denote the SPI controller
type. Use an aptly named variable for that purpose.

Once this patch is merged, the chipset/programmer init functions can set
supported flash chip types and flashrom can automatically select only
matching probe/read/erase/write functions. A side benefit of that will
be the elimination of the Winbond W29EE011 vs. AMIC A49LF040A conflict.

Corresponding to flashrom svn r556.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
Carl-Daniel Hailfinger 2009-05-31 17:57:34 +00:00
parent ebd7b83939
commit 1dfe0ff174
9 changed files with 270 additions and 85 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
chipset_enable.c
View File

@ -42,8 +42,7 @@ unsigned long flashbase = 0;
* Eventually, this will become an array when multiple flash support works.
*/
flashbus_t flashbus = BUS_TYPE_LPC;
void *spibar = NULL;
enum chipbustype buses_supported = CHIP_BUSTYPE_UNKNOWN;
extern int ichspi_lock;
@ -218,7 +217,7 @@ static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
mmio_readw(spibar + 0x6c));
flashbus = BUS_TYPE_VIA_SPI;
spi_controller = SPI_CONTROLLER_VIA;
ich_init_opcodes();
return 0;
@ -269,17 +268,17 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
switch (ich_generation) {
case 7:
flashbus = BUS_TYPE_ICH7_SPI;
spi_controller = SPI_CONTROLLER_ICH7;
spibar_offset = 0x3020;
break;
case 8:
flashbus = BUS_TYPE_ICH9_SPI;
spi_controller = SPI_CONTROLLER_ICH9;
spibar_offset = 0x3020;
break;
case 9:
case 10:
default: /* Future version might behave the same */
flashbus = BUS_TYPE_ICH9_SPI;
spi_controller = SPI_CONTROLLER_ICH9;
spibar_offset = 0x3800;
break;
}
@ -290,8 +289,8 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
/* Assign Virtual Address */
spibar = rcrb + spibar_offset;
switch (flashbus) {
case BUS_TYPE_ICH7_SPI:
switch (spi_controller) {
case SPI_CONTROLLER_ICH7:
printf_debug("0x00: 0x%04x (SPIS)\n",
mmio_readw(spibar + 0));
printf_debug("0x02: 0x%04x (SPIC)\n",
@ -329,7 +328,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
}
ich_init_opcodes();
break;
case BUS_TYPE_ICH9_SPI:
case SPI_CONTROLLER_ICH9:
tmp2 = mmio_readw(spibar + 4);
printf_debug("0x04: 0x%04x (HSFS)\n", tmp2);
printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1));
@ -729,7 +728,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
}
if (has_spi)
flashbus = BUS_TYPE_SB600_SPI;
spi_controller = SPI_CONTROLLER_SB600;
/* Read ROM strap override register. */
OUTB(0x8f, 0xcd6);

2
dummyflasher.c
View File

@ -29,7 +29,7 @@
int dummy_init(void)
{
printf_debug("%s\n", __func__);
flashbus = BUS_TYPE_DUMMY_SPI;
spi_controller = SPI_CONTROLLER_DUMMY;
return 0;
}

39
flash.h
View File

@ -120,9 +120,21 @@ uint32_t chip_readl(const chipaddr addr);
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
enum chipbustype {
CHIP_BUSTYPE_PARALLEL = 1 << 0,
CHIP_BUSTYPE_LPC = 1 << 1,
CHIP_BUSTYPE_FWH = 1 << 2,
CHIP_BUSTYPE_SPI = 1 << 3,
CHIP_BUSTYPE_NONSPI = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH,
CHIP_BUSTYPE_UNKNOWN = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI,
};
struct flashchip {
const char *vendor;
const char *name;
enum chipbustype bustype;
/*
* With 32bit manufacture_id and model_id we can cover IDs up to
* (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's
@ -592,25 +604,12 @@ int board_flash_enable(const char *vendor, const char *part);
void print_supported_boards(void);
/* chipset_enable.c */
extern enum chipbustype buses_supported;
int chipset_flash_enable(void);
void print_supported_chipsets(void);
extern unsigned long flashbase;
typedef enum {
BUS_TYPE_LPC,
BUS_TYPE_ICH7_SPI,
BUS_TYPE_ICH9_SPI,
BUS_TYPE_IT87XX_SPI,
BUS_TYPE_SB600_SPI,
BUS_TYPE_VIA_SPI,
BUS_TYPE_WBSIO_SPI,
BUS_TYPE_DUMMY_SPI
} flashbus_t;
extern flashbus_t flashbus;
extern void *spibar;
/* physmap.c */
void *physmap(const char *descr, unsigned long phys_addr, size_t len);
void physunmap(void *virt_addr, size_t len);
@ -691,6 +690,18 @@ int coreboot_init(void);
extern char *lb_part, *lb_vendor;
/* spi.c */
enum spi_controller {
SPI_CONTROLLER_NONE,
SPI_CONTROLLER_ICH7,
SPI_CONTROLLER_ICH9,
SPI_CONTROLLER_IT87XX,
SPI_CONTROLLER_SB600,
SPI_CONTROLLER_VIA,
SPI_CONTROLLER_WBSIO,
SPI_CONTROLLER_DUMMY,
};
extern enum spi_controller spi_controller;
extern void *spibar;
int probe_spi_rdid(struct flashchip *flash);
int probe_spi_rdid4(struct flashchip *flash);
int probe_spi_rems(struct flashchip *flash);

172
flashchips.c
View File

File diff suppressed because it is too large Load Diff

28
ichspi.c
View File

@ -223,15 +223,15 @@ static int generate_opcodes(OPCODES * op)
return -1;
}
switch (flashbus) {
case BUS_TYPE_ICH7_SPI:
case BUS_TYPE_VIA_SPI:
switch (spi_controller) {
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_VIA:
preop = REGREAD16(ICH7_REG_PREOP);
optype = REGREAD16(ICH7_REG_OPTYPE);
opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
break;
case BUS_TYPE_ICH9_SPI:
case SPI_CONTROLLER_ICH9:
preop = REGREAD16(ICH9_REG_PREOP);
optype = REGREAD16(ICH9_REG_OPTYPE);
opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
@ -305,15 +305,15 @@ int program_opcodes(OPCODES * op)
}
printf_debug("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
switch (flashbus) {
case BUS_TYPE_ICH7_SPI:
case BUS_TYPE_VIA_SPI:
switch (spi_controller) {
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_VIA:
REGWRITE16(ICH7_REG_PREOP, preop);
REGWRITE16(ICH7_REG_OPTYPE, optype);
REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]);
break;
case BUS_TYPE_ICH9_SPI:
case SPI_CONTROLLER_ICH9:
REGWRITE16(ICH9_REG_PREOP, preop);
REGWRITE16(ICH9_REG_OPTYPE, optype);
REGWRITE32(ICH9_REG_OPMENU, opmenu[0]);
@ -599,12 +599,12 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
static int run_opcode(OPCODE op, uint32_t offset,
uint8_t datalength, uint8_t * data)
{
switch (flashbus) {
case BUS_TYPE_VIA_SPI:
switch (spi_controller) {
case SPI_CONTROLLER_VIA:
return ich7_run_opcode(op, offset, datalength, data, 16);
case BUS_TYPE_ICH7_SPI:
case SPI_CONTROLLER_ICH7:
return ich7_run_opcode(op, offset, datalength, data, 64);
case BUS_TYPE_ICH9_SPI:
case SPI_CONTROLLER_ICH9:
return ich9_run_opcode(op, offset, datalength, data);
default:
printf_debug("%s: unsupported chipset\n", __FUNCTION__);
@ -688,7 +688,7 @@ int ich_spi_read(struct flashchip *flash, uint8_t * buf)
int page_size = flash->page_size;
int maxdata = 64;
if (flashbus == BUS_TYPE_VIA_SPI) {
if (spi_controller == SPI_CONTROLLER_VIA) {
maxdata = 16;
}
@ -723,7 +723,7 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf)
break;
}
if (flashbus == BUS_TYPE_VIA_SPI)
if (spi_controller == SPI_CONTROLLER_VIA)
maxdata = 16;
for (j = 0; j < erase_size / page_size; j++) {

2
it87spi.c
View File

@ -101,7 +101,7 @@ int it87xx_probe_spi_flash(const char *name)
it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2);
if (it8716f_flashport)
flashbus = BUS_TYPE_IT87XX_SPI;
spi_controller = SPI_CONTROLLER_IT87XX;
return (!it8716f_flashport);
}

8
sb600spi.c
View File

@ -25,7 +25,7 @@
#include "flash.h"
#include "spi.h"
typedef struct _spi_controller {
struct sb600_spi_controller {
unsigned int spi_cntrl0; /* 00h */
unsigned int restrictedcmd1; /* 04h */
unsigned int restrictedcmd2; /* 08h */
@ -34,9 +34,9 @@ typedef struct _spi_controller {
unsigned int spi_cmdvalue1; /* 14h */
unsigned int spi_cmdvalue2; /* 18h */
unsigned int spi_fakeid; /* 1Ch */
} sb600_spi_controller;
};
sb600_spi_controller *spi_bar = NULL;
struct sb600_spi_controller *spi_bar = NULL;
uint8_t *sb600_spibar;
int sb600_spi_read(struct flashchip *flash, uint8_t *buf)
@ -114,7 +114,7 @@ int sb600_spi_command(unsigned int writecnt, unsigned int readcnt,
writecnt--;
spi_bar = (sb600_spi_controller *) sb600_spibar;
spi_bar = (struct sb600_spi_controller *) sb600_spibar;
printf_debug("%s, cmd=%x, writecnt=%x, readcnt=%x\n",
__func__, cmd, writecnt, readcnt);

83
spi.c
View File

@ -26,24 +26,27 @@
#include "flash.h"
#include "spi.h"
enum spi_controller spi_controller = SPI_CONTROLLER_NONE;
void *spibar = NULL;
void spi_prettyprint_status_register(struct flashchip *flash);
int spi_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
switch (flashbus) {
case BUS_TYPE_IT87XX_SPI:
switch (spi_controller) {
case SPI_CONTROLLER_IT87XX:
return it8716f_spi_command(writecnt, readcnt, writearr,
readarr);
case BUS_TYPE_ICH7_SPI:
case BUS_TYPE_ICH9_SPI:
case BUS_TYPE_VIA_SPI:
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_ICH9:
case SPI_CONTROLLER_VIA:
return ich_spi_command(writecnt, readcnt, writearr, readarr);
case BUS_TYPE_SB600_SPI:
case SPI_CONTROLLER_SB600:
return sb600_spi_command(writecnt, readcnt, writearr, readarr);
case BUS_TYPE_WBSIO_SPI:
case SPI_CONTROLLER_WBSIO:
return wbsio_spi_command(writecnt, readcnt, writearr, readarr);
case BUS_TYPE_DUMMY_SPI:
case SPI_CONTROLLER_DUMMY:
return dummy_spi_command(writecnt, readcnt, writearr, readarr);
default:
printf_debug
@ -122,10 +125,10 @@ int spi_write_enable(void)
if (result)
printf_debug("%s failed", __func__);
if (result == SPI_INVALID_OPCODE) {
switch (flashbus) {
case BUS_TYPE_ICH7_SPI:
case BUS_TYPE_ICH9_SPI:
case BUS_TYPE_VIA_SPI:
switch (spi_controller) {
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_ICH9:
case SPI_CONTROLLER_VIA:
printf_debug(" due to SPI master limitation, ignoring"
" and hoping it will be run as PREOP\n");
return 0;
@ -202,13 +205,13 @@ int probe_spi_rdid(struct flashchip *flash)
int probe_spi_rdid4(struct flashchip *flash)
{
/* only some SPI chipsets support 4 bytes commands */
switch (flashbus) {
case BUS_TYPE_ICH7_SPI:
case BUS_TYPE_ICH9_SPI:
case BUS_TYPE_VIA_SPI:
case BUS_TYPE_SB600_SPI:
case BUS_TYPE_WBSIO_SPI:
case BUS_TYPE_DUMMY_SPI:
switch (spi_controller) {
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_ICH9:
case SPI_CONTROLLER_VIA:
case SPI_CONTROLLER_SB600:
case SPI_CONTROLLER_WBSIO:
case SPI_CONTROLLER_DUMMY:
return probe_spi_rdid_generic(flash, 4);
default:
printf_debug("4b ID not supported on this SPI controller\n");
@ -281,7 +284,7 @@ uint8_t spi_read_status_register(void)
int ret;
/* Read Status Register */
if (flashbus == BUS_TYPE_SB600_SPI) {
if (spi_controller == SPI_CONTROLLER_SB600) {
/* SB600 uses a different way to read status register. */
return sb600_read_status_register();
} else {
@ -569,10 +572,10 @@ int spi_write_status_enable(void)
if (result)
printf_debug("%s failed", __func__);
if (result == SPI_INVALID_OPCODE) {
switch (flashbus) {
case BUS_TYPE_ICH7_SPI:
case BUS_TYPE_ICH9_SPI:
case BUS_TYPE_VIA_SPI:
switch (spi_controller) {
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_ICH9:
case SPI_CONTROLLER_VIA:
printf_debug(" due to SPI master limitation, ignoring"
" and hoping it will be run as PREOP\n");
return 0;
@ -651,16 +654,16 @@ int spi_nbyte_read(int address, uint8_t *bytes, int len)
int spi_chip_read(struct flashchip *flash, uint8_t *buf)
{
switch (flashbus) {
case BUS_TYPE_IT87XX_SPI:
switch (spi_controller) {
case SPI_CONTROLLER_IT87XX:
return it8716f_spi_chip_read(flash, buf);
case BUS_TYPE_SB600_SPI:
case SPI_CONTROLLER_SB600:
return sb600_spi_read(flash, buf);
case BUS_TYPE_ICH7_SPI:
case BUS_TYPE_ICH9_SPI:
case BUS_TYPE_VIA_SPI:
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_ICH9:
case SPI_CONTROLLER_VIA:
return ich_spi_read(flash, buf);
case BUS_TYPE_WBSIO_SPI:
case SPI_CONTROLLER_WBSIO:
return wbsio_spi_read(flash, buf);
default:
printf_debug
@ -699,16 +702,16 @@ int spi_chip_write_1(struct flashchip *flash, uint8_t *buf)
*/
int spi_chip_write_256(struct flashchip *flash, uint8_t *buf)
{
switch (flashbus) {
case BUS_TYPE_IT87XX_SPI:
switch (spi_controller) {
case SPI_CONTROLLER_IT87XX:
return it8716f_spi_chip_write_256(flash, buf);
case BUS_TYPE_SB600_SPI:
case SPI_CONTROLLER_SB600:
return sb600_spi_write_1(flash, buf);
case BUS_TYPE_ICH7_SPI:
case BUS_TYPE_ICH9_SPI:
case BUS_TYPE_VIA_SPI:
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_ICH9:
case SPI_CONTROLLER_VIA:
return ich_spi_write_256(flash, buf);
case BUS_TYPE_WBSIO_SPI:
case SPI_CONTROLLER_WBSIO:
return wbsio_spi_write_1(flash, buf);
default:
printf_debug
@ -731,8 +734,8 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf)
unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]};
int result;
switch (flashbus) {
case BUS_TYPE_WBSIO_SPI:
switch (spi_controller) {
case SPI_CONTROLLER_WBSIO:
fprintf(stderr, "%s: impossible with Winbond SPI masters,"
" degrading to byte program\n", __func__);
return spi_chip_write_1(flash, buf);

2
wbsio_spi.c
View File

@ -63,7 +63,7 @@ int wbsio_check_for_spi(const char *name)
return 1;
printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase);
flashbus = BUS_TYPE_WBSIO_SPI;
spi_controller = SPI_CONTROLLER_WBSIO;
return 0;
}