mirror of
https://review.coreboot.org/flashrom.git
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f8555e24a4
If we only send an opcode and no additional data/address, the SPI controller will read one byte too few from the chip. Basically, the last byte of the chip response is discarded and will not end up in the FIFO. It is unclear if the CS# line is set high too early as well. That hardware bug is undocumented as of now, but I'm working with AMD to add a detailed description of it to the errata. Add loads of additional debugging to SB600/SB700 init. Add explanatory comments for unintuitive code flow. Thanks go to Uwe for testing quite a few iterations of the patch. Kill the SB600 flash chip status register special case, which was a somewhat misguided workaround for that hardware erratum. Note for future added features in the SB600 SPI driver: It may be possible to read up to 15 bytes of command response with overlapping reads due to the ring buffer design of the FIFO if the command can be repeated without ill effects. Same for skipping up to 7 bytes between command and response. Corresponding to flashrom svn r661. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de>
-------------------------------------------------------------------------------
flashrom README
-------------------------------------------------------------------------------
flashrom is a utility for reading, writing, verifying and erasing flash ROM
chips. It's often used to flash BIOS/EFI/coreboot/firmware images in-system
using a supported mainboard, but it also supports flashing of network
cards (NICs), SATA controller cards, and other external devices which can
program flash chips.
It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and
TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash,
or SPI.
(see http://coreboot.org for details on coreboot)
Packaging
---------
To package flashrom and remove dependencies on subversion, either use
make export
or
make tarball
make export will export all flashrom files from the subversion repository at
revision BASE into a directory named $EXPORTDIR/flashrom-$VERSION-r$SVNREVISION
and will additionally modify the Makefile in that directory to contain the svn
revision of the exported tree.
make tarball will simply tar up the result of make export and gzip compress it.
The snapshot tarballs are the result of make tarball and require no further
processing.
Build Instructions
------------------
To build flashrom you need to install the following packages or ports:
Linux et al:
* pciutils
* pciutils-devel / pciutils-dev / libpci-dev
* zlib-devel / zlib1g-dev
On FreeBSD, you need the following ports:
* devel/gmake
* devel/libpci
To compile on Linux, use:
make
To compile on FreeBSD, use:
gmake
To compile on Solaris, use:
gmake LDFLAGS="-L$pathtolibpci -lpci -lz" CC="gcc -I$pathtopciheaders" \
CFLAGS=-O2
To compile on DragonFly BSD, use:
ln -s /usr/pkg/include/pciutils pci
gmake CFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -lpci -lz"
To compile and run on Darwin/Mac OS X:
Install DirectIO from coresystems GmbH.
DirectIO is available at http://www.coresystems.de/en/directio.
Installation
------------
In order to install flashrom and the manpage into /usr/local, type:
sudo make install
For installation in a different directory use DESTDIR, e.g. like this:
sudo make DESTDIR=/usr install
Usage / Options
---------------
Please see the flashrom(8) manpage.
Exit status
-----------
Please see the flashrom(8) manpage.
coreboot Table and Mainboard Identification
--------------------------------------------
Please see the flashrom(8) manpage.
ROM Layout Support
------------------
Please see the flashrom(8) manpage.
Supported Flash Chips / Chipsets / Mainboards
---------------------------------------------
Please check the output of 'flashrom -L' for the list of supported
flash chips, chipsets/southbridges, mainboards, and flash programmers.
Website
-------
The official flashrom website is:
http://coreboot.org/Flashrom