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39 Commits

Author SHA1 Message Date
Guillaume Chatelet
a6d219bed7 Fixes #102 - wrong macros 2020-01-29 11:00:11 +01:00
Patrick Siegl
3d71a964f5 Use a getter function to avoid manual work for future to-be-added cpu features 2020-01-06 16:24:10 +01:00
Moxeja
73a121b1ae Differentiate between different Lake uarch 2020-01-06 16:23:29 +01:00
Tamas Zsoldos
d835b4958c Update features for AArch64. 
Add all missing features up to Linux v5.0.

Features added: evtstrm, atomics, fphp, asimdhp, cpuid, asimdrdm,
jscvt, fcma, lrcpc, dcpop, sha3, sm3, sm4, asimddp, sha512, sve,
asimdfhm, dit, uscat, ilrcpc, flagm, ssbs, sb, paca, pacg.
 2019-10-11 11:02:00 +02:00
Artem Alekseev
653d581e03 Add support for leaf2 and leaf4 on Intel's x86 arch (#80) 
* Add support for leaf4 on Intel's x86 arch
* Update cpuinfo_x86.h
* Fix typo
* Force compiler to use C99
* Add Intel x86 leaf2 support
* Fixes after review
* Fix review comments
 2019-07-02 16:52:25 +02:00
Dr.-Ing. Patrick Siegl
bfd109b687 Completed all missing ARM hwcaps. (#79) 2019-06-26 12:56:52 +02:00
Artem Alekseev
bfb4cf99cc Add CpuIdEx function to pass inputs in ecx register (required for E.g. leaf4) (#77) 2019-06-21 14:13:29 +02:00
Artem Alekseev
3ee4a9e801 Support x86 DCA and SS features (#76) 
* Add dca and ss features
* Remove trailing white spaces
 2019-06-19 15:06:05 +02:00
Dr.-Ing. Patrick Siegl
6482bad213 Added RPI zero with its features HALF, THUMB, FASTMULT, EDSP, JAVA and TLS (#75) 2019-06-18 12:53:08 +02:00
Dr.-Ing. Patrick Siegl
367bc42116 Support x86 features: FPU, TSC, CX8, CLFSH, MMX, VAES, HLE, RTM, RDSEED, CLFLUSHOPT, CLWB, SSE, SSE2, SSE3, PCLMULQDQ (#73) 2019-06-13 11:53:39 +02:00
Guillaume Chatelet
d395dfa026
Add x86 missing feature detections for ndk_compat (#58) 
One more step towards #47.
 2019-01-22 13:19:42 +01:00
Guillaume Chatelet
5911e96bbd
add r6 flag (#57) 
Update tests and add support in ndk-compat as well
 2019-01-22 11:00:48 +01:00
Guillaume Chatelet
9917e8481e
Fix hwcaps constants for mips. (#60) 
fixes #59
 2019-01-21 10:39:24 +01:00
Guillaume Chatelet
4155ee7e36
Guarding header use with architecture (#56) 2019-01-18 13:38:22 +01:00
Guillaume Chatelet
dfdac6adfc
Add partial implementation of ndk_compat (#54) 
* First implementation of ndk_compat
* Restrict building of linux_based_hardware_detection to UNIX
* Fix variable declaration and printf formatting
* Restrict ndk compat to UNIX style systems
* Restrict cpu_mask index to 32
* Fix values display in ndk-compat-test
* Addressing comments
 2019-01-17 18:00:21 +01:00
Guillaume Chatelet
918553a21f Export GetArmCpuId function 2019-01-17 15:28:04 +01:00
Guillaume Chatelet
fc7efb4c14 Fix Mips32 and add an alias for Mips32/64. 2019-01-16 14:26:18 +01:00
Guillaume Chatelet
d864585dc9 Update macros to detect mips64 and differentiate between x86 32/64. 2019-01-16 14:02:24 +01:00
fuzun
f6c8a5d92d Revert "Different approach for -1 & true compliance" 
This reverts commit 58a232c560cbd5d341aeb67b890cbe263528a755.
 2018-09-11 17:24:35 +03:00
fuzun
58a232c560 Different approach for -1 & true compliance 2018-09-08 05:56:35 +03:00
fuzun
f189298f4f Revert "Change feature variables to unsigned int to fully comply with 'true' and 'false' & IsBitSet()" 
This reverts commit 319bd6f26be9232cc534e376f1d1ce50505394c2.
 2018-09-08 05:16:00 +03:00
fuzun
68462fb78f Suppress analysis warning 2018-08-30 06:22:54 +03:00
fuzun
319bd6f26b Change feature variables to unsigned int to fully comply with 'true' and 'false' & IsBitSet() 
It seems that ' : 1' alignments cause signed integers to be either -1 or 0. While -1 is true and 0 is false reverse might not be always correct when true is defined 1.

Maybe change feature variables to bool ?
 2018-08-30 06:11:35 +03:00
Guillaume Chatelet
26133d3b62 Match function definition and declaration arguments. 2018-06-20 09:18:57 +02:00
Guillaume Chatelet
d5e3985359
Delete .cpuinfo_ppc.h.swp 2018-05-15 10:46:12 +02:00
Rashmica Gupta
c45e32f812
powerpc: Add AT_PLATFORM and AT_BASE_PLATFORM 
Some PowerPC machines can operate in a mode that appears different
to a process than the actual hardware. AT_PLATFORM indicates the
supported instruction set and AT_BASE_PLATFORM indicates the
actual microarchitecture of the hardware.

Signed-off-by: Rashmica Gupta <rashmica.gupta@au1.ibm.com>
 2018-05-15 14:24:58 +10:00
Rashmica Gupta
1c8bf0ecd8
hwcaps: Change uint32_t to unsigned long 
getauxval() returns an unsigned long which can be defined to be
more than 32 bits so don't force the result into a uint32_t.

Signed-off-by: Rashmica Gupta <rashmica.gupta@au1.ibm.com>
 2018-05-15 14:24:53 +10:00
Rashmica Gupta
3adafbfe66
powerpc: Added PowerPC implementation 
Signed-off-by: Rashmica Gupta <rashmica.gupta@au1.ibm.com>
 2018-05-15 14:24:45 +10:00
Arvid Gerstmann
d968991caa Reformat files 2018-05-04 09:32:17 +02:00
Arvid Gerstmann
a1ffdcbe70 Explicitly namespace every extern identifier 2018-04-26 10:31:03 +02:00
Guillaume Chatelet
9b872ce0b2 Add cx16 (cmpxchg16b) cpuid flag. Fixes #30 2018-03-13 10:58:42 +01:00
Patrik Fiedler
3ee0d62e87
detect intel sgx and smx cpu features for the x86 arch 2018-02-13 11:16:48 +01:00
Guillaume Chatelet
e419573d10 Use CPU_FEATURES_ prefix for namespace macros. 2018-02-12 16:15:15 +01:00
Guillaume Chatelet
11e3e20496 Reverting 338484f6f2176c3d8ede0ed2f3fbd6cf1eb0274c. Fixes #2 2018-02-09 08:55:11 +01:00
Guillaume Chatelet
1d6ba6139c
Merge pull request #5 from bsurmanski/patch-1 
Fix spelling mistake for 'Cannon Lake'
 2018-02-08 16:34:15 +01:00
Guillaume Chatelet
338484f6f2 Fixes #2 - vpclmulqdq should be pclmulqdq. 2018-02-08 11:35:31 +01:00
Brandon Surmanski
efcc49a493
Fix spelling mistake for 'Cannon Lake' 
See:
https://www.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/platform-codenames.html
https://en.wikipedia.org/wiki/Cannon_Lake_(microarchitecture)
 2018-02-07 11:07:00 -08:00
Guillaume Chatelet
8e58ef0d2b Removing THIRD_PARTY_ from C headers. 2018-02-01 10:38:48 +01:00
Guillaume Chatelet
439d371594 Adding code. Closes #0. 2018-02-01 10:03:09 +01:00