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mirror of https://github.com/google/cpu_features.git synced 2025-04-29 07:53:37 +02:00

65 Commits

Author SHA1 Message Date
Guillaume Chatelet
e63405f118
Remove need for utsname (#136) 2020-10-09 20:40:06 +00:00
Guillaume Chatelet
4795373db2
Fix SSE detection on non-AVX CPUs (#135)
Fixes #4. This is based on #115 with a few modifications:
 - Removed use of __builtin_cpu_supports since it relies on cpuid and doesn't improve on the current situation,
 - Added detection for all of sse, sse2, sse3, ssse3, sse4_1 and sse4_2,
 - Added tests for Atom, Nehalem, and P3 processors,

Thx to @gadoofou87 for providing the original PR.
It also removes the need for #92

* Fix SSE detection on non-AVX CPUs
* Fixes typo
* Mock OSX sysctlbyname in tests
* Also update other tests
* FakeCpu is reset between each tests
* Fix conflicting name on Windows
* Disable pre AVX cpu sse detection tests on Windows
* Guard OS specific code with macros
* Fix missing import for tests
* Fix wrong function prototype
* Fix wrong mocking of P3 on Windows
* Completely guard OS specific parts in x86 tests
* Store DWORD instead unsigned long for x86 tests
2020-10-09 15:20:25 +00:00
Guillaume Chatelet
22a5362e11
[NFC] clang-format codebase (#134)
* [NFC] clang-format codebase

* revert to 80 char columns at the price of uglier table init

* Specifically disabling clang-format for table initialization
2020-09-23 09:52:20 +00:00
Jeff Hammond
17ffb65117
detect AVX-512 FMA count (#125)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* second FMA features - incomplete and wrong

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* oops: use T/F not 2/1

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* implement SKX lookup

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

* cleanup AVX512 second FMA code

1) remove debug stuff
2) remove ICX - will add details when available

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* fix CPX detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove elses

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove curly braces from single-line conditional bodies

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* apply clang-format

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

Fixes #120
2020-09-22 07:29:46 +00:00
Guillaume Chatelet
76dafc7e3b
[NFC] Remove unused max_cpuid_leaf variable (#131) 2020-09-21 14:54:13 +02:00
Jeff Hammond
33bd72c1bc
detect future Intel AVX/AMX features (#124)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AVX512_BF16 and AVX512_VP2INTERSECT detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* correction for KNM features: s/4VBMI2/4FMAPS/g

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AMX/TMUL bits from 319433-040

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fixes #128
2020-09-21 07:56:26 +00:00
Jeff Hammond
e698327713
add future Intel microarchitectures (#123)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fix #127
2020-09-21 07:54:58 +00:00
Tamas Zsoldos
73d10ad25b
Update features for AArch64 to Linux 5.8 (#122)
This adds the following features: dcpodp, sve2, sveaes, svepmull,
svebitperm, svesha3, svesm4, flagm2, frint, svei8mm, svef32mm,
svef64mm, svebf16, i8mm, bf16, dgh and rng.

With these, all features used by Linux 5.8 on AArch64 is supported.

Fixes #126
2020-09-21 07:50:38 +00:00
Corentin Le Molgat
339bfd32be Add OsSupport structure 2020-03-12 10:58:41 +00:00
Corentin Le Molgat
404e462cd4 Move AMD extra flags to its own function 2020-03-12 10:58:41 +00:00
gadoofou87
3262a55118 Support x86 FMA4 and SSE4A features 2020-03-12 10:58:41 +00:00
Guillaume Chatelet
5d55aa1efe
Add cache_info data to X86 for list_cpu_features (#105)
* Add cache_info data to X86 for list_cpu_features
2020-01-29 15:02:48 +01:00
Guillaume Chatelet
e50d7db3b0 [NFC] Use Designated Initializers 2020-01-29 11:31:10 +01:00
Moxeja
24b8a1de17 Add INTEL_WHL and INTEL_ICL to uarch get name function 2020-01-07 10:18:04 +01:00
Patrick Siegl
3d71a964f5 Use a getter function to avoid manual work for future to-be-added cpu features 2020-01-06 16:24:10 +01:00
Moxeja
73a121b1ae Differentiate between different Lake uarch 2020-01-06 16:23:29 +01:00
Guillaume Chatelet
8a6fd87074 [NFC] Fixed signed shift
signed shift result (0x80000000) sets the sign bit of the shift expression's type ('int') and becomes negative
2019-11-13 14:39:06 +01:00
Guillaume Chatelet
99d2363c62 [NFC] fix various errors 2019-11-13 11:22:31 +01:00
Guillaume Chatelet
be306b7b15 [NFC] fix unused and shadowing variables 2019-11-13 11:15:40 +01:00
Guillaume Chatelet
9d2de7fb5c Making sure global variable is aligned without using attributes 2019-11-12 17:12:44 +01:00
Guillaume Chatelet
7298eda2ff Making sure global variable is 8B aligned as well 2019-11-12 16:53:04 +01:00
Guillaume Chatelet
0f2f60ab00 Address comments in https://github.com/google/cpu_features/pull/94 2019-11-12 16:26:00 +01:00
Guillaume Chatelet
64b1b9090f [NFC] Use a tree structure in list_cpu_features
This is in preparation to include cache hierarchy in the dumped data.
2019-11-12 14:00:19 +01:00
Tamas Zsoldos
d835b4958c Update features for AArch64.
Add all missing features up to Linux v5.0.

Features added: evtstrm, atomics, fphp, asimdhp, cpuid, asimdrdm,
jscvt, fcma, lrcpc, dcpop, sha3, sm3, sm4, asimddp, sha512, sve,
asimdfhm, dit, uscat, ilrcpc, flagm, ssbs, sb, paca, pacg.
2019-10-11 11:02:00 +02:00
Dr.-Ing. Patrick Siegl
22c05ed620 Use enum properly to directly access kConfig struct 2019-07-04 21:25:14 +02:00
Leonard Mosescu
bdb36d9489 Fix a few compile warnings (#84)
Visual C++ reported a number of warnings:

..\src\filesystem.c(27): warning C4996: '_open': This function or variable may be unsafe. Consider using _sopen_s instead. To disable deprecation, use _CRT_SECURE_NO_WARNINGS. See online help for details.
..\src\filesystem.c(34): warning C4267: 'function': conversion from 'size_t' to 'unsigned int', possible loss of data
..\src\string_view.c(25): warning C4244: 'return': conversion from '__int64' to 'int', possible loss of data
..\src\string_view.c(41): warning C4244: 'return': conversion from '__int64' to 'int', possible loss of data
..\src\utils\list_cpu_features.c(151): warning C4090: 'function': different 'const' qualifiers
..\src\cpuinfo_x86.c(67): warning C4244: 'return': conversion from 'unsigned __int64' to 'uint32_t', possible loss of data
..\test\filesystem_for_testing.cc(48): warning C4267: 'return': conversion from 'size_t' to 'int', possible loss of data
..\test\filesystem_for_testing.cc(57): warning C4267: 'argument': conversion from 'size_t' to 'int', possible loss of data
..\test\bit_utils_test.cc(26): warning C4267: 'argument': conversion from 'size_t' to 'uint32_t', possible loss of data
..\test\bit_utils_test.cc(32): warning C4267: 'argument': conversion from 'size_t' to 'uint32_t', possible loss of data
..\test\bit_utils_test.cc(37): warning C4267: 'argument': conversion from 'size_t' to 'uint32_t', possible loss of data

Most of them, with the exception of _open() -> _sopen_s() are about
questionable implicit casts. Fixing the types and adding explicit casts
to explicitly mark the intention (and silence the warnings in the process)
2019-07-03 14:57:19 +02:00
Artem Alekseev
653d581e03 Add support for leaf2 and leaf4 on Intel's x86 arch (#80)
* Add support for leaf4 on Intel's x86 arch
* Update cpuinfo_x86.h
* Fix typo
* Force compiler to use C99
* Add Intel x86 leaf2 support
* Fixes after review
* Fix review comments
2019-07-02 16:52:25 +02:00
Dr.-Ing. Patrick Siegl
bfd109b687 Completed all missing ARM hwcaps. (#79) 2019-06-26 12:56:52 +02:00
Dr.-Ing. Patrick Siegl
18342789a1 Fix ARMv6 on Linux vs Android (#81) 2019-06-25 17:58:31 +02:00
Artem Alekseev
bfb4cf99cc Add CpuIdEx function to pass inputs in ecx register (required for E.g. leaf4) (#77) 2019-06-21 14:13:29 +02:00
Artem Alekseev
3ee4a9e801 Support x86 DCA and SS features (#76)
* Add dca and ss features
* Remove trailing white spaces
2019-06-19 15:06:05 +02:00
Dr.-Ing. Patrick Siegl
6482bad213 Added RPI zero with its features HALF, THUMB, FASTMULT, EDSP, JAVA and TLS (#75) 2019-06-18 12:53:08 +02:00
Dr.-Ing. Patrick Siegl
367bc42116 Support x86 features: FPU, TSC, CX8, CLFSH, MMX, VAES, HLE, RTM, RDSEED, CLFLUSHOPT, CLWB, SSE, SSE2, SSE3, PCLMULQDQ (#73) 2019-06-13 11:53:39 +02:00
natanbc
084ec5cd0f Convert XGETBV to equivalent byte form in GetXCR0Eax (#69)
osxcross (https://github.com/tpoechtrager/osxcross) gives the following error, which also happens with regular gcc on OS X (https://github.com/asmjit/asmjit/issues/78):
```
cpu_features/src/cpuinfo_x86.c:44:no such instruction: `XGETBV'
```
2019-03-20 10:04:24 +01:00
Guillaume Chatelet
d395dfa026
Add x86 missing feature detections for ndk_compat (#58)
One more step towards #47.
2019-01-22 13:19:42 +01:00
Guillaume Chatelet
5911e96bbd
add r6 flag (#57)
Update tests and add support in ndk-compat as well
2019-01-22 11:00:48 +01:00
Guillaume Chatelet
9917e8481e
Fix hwcaps constants for mips. (#60)
fixes #59
2019-01-21 10:39:24 +01:00
Guillaume Chatelet
4155ee7e36
Guarding header use with architecture (#56) 2019-01-18 13:38:22 +01:00
Guillaume Chatelet
dfdac6adfc
Add partial implementation of ndk_compat (#54)
* First implementation of ndk_compat
* Restrict building of linux_based_hardware_detection to UNIX
* Fix variable declaration and printf formatting
* Restrict ndk compat to UNIX style systems
* Restrict cpu_mask index to 32
* Fix values display in ndk-compat-test
* Addressing comments
2019-01-17 18:00:21 +01:00
Guillaume Chatelet
918553a21f Export GetArmCpuId function 2019-01-17 15:28:04 +01:00
Guillaume Chatelet
122b067087 Use Cmake macros to detect getauxval and dlopen 2019-01-15 15:18:08 +01:00
Guillaume Chatelet
e8e5610fc4 Per arch build and inlining of cpuid_x86. 2019-01-15 10:52:56 +01:00
fuzun
f6c8a5d92d Revert "Different approach for -1 & true compliance"
This reverts commit 58a232c560cbd5d341aeb67b890cbe263528a755.
2018-09-11 17:24:35 +03:00
fuzun
a23004e154 Merge branch 'master' of https://github.com/fuzun/cpu_features 2018-09-08 06:01:08 +03:00
fuzun
58a232c560 Different approach for -1 & true compliance 2018-09-08 05:56:35 +03:00
fuzun
7c1c91f9ea
Merge pull request #1 from google/master
Sync with head
2018-09-08 05:16:44 +03:00
Guillaume Chatelet
dab7cea707 Fix -Wunused-function warning. 2018-09-07 15:17:44 +02:00
fuzun
9d9134cf0b Parantheses added to CPUID macro 2018-08-30 06:13:02 +03:00
Rashmica Gupta
c45e32f812
powerpc: Add AT_PLATFORM and AT_BASE_PLATFORM
Some PowerPC machines can operate in a mode that appears different
to a process than the actual hardware. AT_PLATFORM indicates the
supported instruction set and AT_BASE_PLATFORM indicates the
actual microarchitecture of the hardware.

Signed-off-by: Rashmica Gupta <rashmica.gupta@au1.ibm.com>
2018-05-15 14:24:58 +10:00
Rashmica Gupta
1c8bf0ecd8
hwcaps: Change uint32_t to unsigned long
getauxval() returns an unsigned long which can be defined to be
more than 32 bits so don't force the result into a uint32_t.

Signed-off-by: Rashmica Gupta <rashmica.gupta@au1.ibm.com>
2018-05-15 14:24:53 +10:00