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Code Issues Releases Wiki Activity

board_enable.c: Port to use pcidev_find_vendorclass() helper

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Change-Id: I3d8e3dbd5eeb057d7c959a82678cca2345fc69d9
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
This commit is contained in:
Edward O'Callaghan 2022-02-26 11:37:08 +11:00 committed by Edward O'Callaghan
parent 0f388acaba
commit 5f0d2aa6c8
1 changed files with 10 additions and 16 deletions
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26
board_enable.c
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@ -1555,26 +1555,20 @@ static int intel_ich_gpio_set(int gpio, int raise)
int i, allowed;
/* First, look for a known LPC bridge */
for (dev = pacc->devices; dev; dev = dev->next) {
uint16_t device_class;
/* libpci before version 2.2.4 does not store class info. */
device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
if ((dev->vendor_id == 0x8086) &&
(device_class == 0x0601)) { /* ISA bridge */
/* Is this device in our list? */
for (i = 0; intel_ich_gpio_table[i].id; i++)
if (dev->device_id == intel_ich_gpio_table[i].id)
break;
if (intel_ich_gpio_table[i].id)
break;
}
}
dev = pcidev_find_vendorclass(0x8086, 0x0601); /* ISA bridge */
if (!dev) {
msg_perr("\nERROR: No known Intel LPC bridge found.\n");
return -1;
}
/* Is this device in our list? */
for (i = 0; intel_ich_gpio_table[i].id; i++)
if (dev->device_id == intel_ich_gpio_table[i].id)
break;
if (!intel_ich_gpio_table[i].id) {
msg_perr("\nERROR: No known Intel LPC bridge found.\n");
return -1;
}
/*
* According to the datasheets, all Intel ICHs have the GPIO bar 5:1