Does exactly what it says on the tin.
BUG=b:220799648
TEST=```localhost ~ # flashrom --flash-name
<snip>
Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
vendor="Programmer" name="Opaque flash chip"
flashrom -p internal --ifd -i fd -i bios -r /tmp/filename.rom
flashrom unknown on Linux 5.15.22 (x86_64)
flashrom is free software, get the source code at https://flashrom.org
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
coreboot table found at 0x768a7000.
Found chipset "Intel Alder Lake-N".
Enabling flash write... Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed.
New value is 0x8b.
SPI Configuration is locked down.
OK.
Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000
/dev/mem mmap failed: Resource temporarily unavailable
Could not map flash chip W25Q256JV_M at 0x00000000fe000000.
Reading ich descriptor... done.
Using regions: "bios", "fd".
Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000
/dev/mem mmap failed: Resource temporarily unavailable
Could not map flash chip W25Q256JV_M at 0x00000000fe000000.
Reading flash... done.
SUCCESS
Also,
Reading ich descriptor... Reading 4096 bytes starting at 0x000000.
done.
Assuming chipset '600 series Alder Point'.
Added layout entry 00000000 - 00000fff named fd
Added layout entry 00500000 - 01ffffff named bios
Added layout entry 00001000 - 004fffff named me
```
Tested on Nivviks/ADL-N and Brya/ADL-P.
Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Elkhart Lake has a chipset called Mule Creek Canyon which is quite
compatible with 300 series chipsets. There are a few differences though,
e.g. different encoding for the SPI clock values for read and write in
the FLCOMP register. In addition Elkhart Lake has a new PCI device ID
for the SPI controller which is added, too.
TEST=Read and flash complete flash on Siemens MC EHL1
Change-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tiger Lake has very low ICCRIBA (TGL=0x11, CNL=0x34 and CML=0x34) and
detects as unknown chipset compatible with 300 series chipset. Add a
new enum CHIPSET_500_SERIES_TIGER_POINT and treat it identically to
CHIPSET_400_SERIES_COMET_POINT. There are some exceptions though,
ICCRIBA is no longer present n descriptor content so a new union has
been defined for new fields and used in descriptor guessing.
freq_read field is not present on Tiger Lake, moreover in CannonPoint
and Comet Point this field is used as eSPI/EC frequency, so a new
function to print read frequency has ben added. Finally Tiger lake
boot straps include eSPI, so a new bus has been added for the new
straps.
TEST=Flash BIOS region on Intel i5-1135G7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I28f3b6fe9f8ce9e976a6808683f46b6f4ec72bdd
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55578
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mosys is dropping the eventlog command, in favor of the elogtool
command provided in coreboot. The output is compatible with what
mosys used to output.
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I8c4be82fed28b6a19746e6b93fafce23bd8ede5d
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
ich_descriptors_tool/Makefile: have the same behavior as the main
flashrom Makefile
- only set gcc explicit on MinGW HOST_OS
- don't fallback to gcc if CC was not set
- set CFLAGS and EXEC_SUFFIX for TARGET_OS, not for HOST_OS
Change-Id: I353c3de250167994a4aea1edfef57d839e900d78
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move the test code for OS detection in a extra directory to split it
from the main flashrom code.
Change-Id: Id911f17f4100f242e1fde10d23a8459ddf38b369
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a Nix shell file which is able to compile flashrom.
Change-Id: I9757b952f4b034e98c2b4b70fbede52d8efb9d50
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This allows MinGW targets to use certain printf formatting
identifiers such as "%v" by adding -D__USE_MINGW_ANSI_STDIO=1 to
the CFLAGS. This is also done in flashrom's top-level Makefile.
Reported on https://github.com/flashrom/flashrom/issues/149
Change-Id: I644be8b5b607cc77b4be2121c443f0d41d8da687
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/43052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The SPI hardware is pretty much unchanged from Apollo Lake. However, the
IFD differs significantly enough to require special handling.
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change removes --ignore-fmap as this is implicitly computed based
on other supplied options by the user.
Original-Signed-off-by: Daniel Campello <campello@chromium.org>
Original-Cq-Depend: chromium:2854174, chrome-internal:3789445, chromium:2854014
Original-Change-Id: I841a56d8726644cedd7d616ddfd5656b92dd7e59
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2851658
Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
(cherry picked from commit 2e2a5e449229e9c9604235a98b56e5dd29bf25cf)
Change-Id: Ib329f3adb59ce1848d1540844d64b968f49eb22a
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52890
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We can just use the libc functions directly. This is exactly what nix
does anyway.
BUG=none
TEST=unit tests
BRANCH=none
Original-Change-Id: I45c02f0c71d164bd8f504fe2b8d3acd54e0d5704
Original-Signed-off-by: Chirantan Ekbote <chirantan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2560393
Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Original-Reviewed-by: Allen Webb <allenwebb@google.com>
Original-Commit-Queue: Allen Webb <allenwebb@google.com>
(cherry picked from commit 1ba7dbe83e01d270b6d8d597a079ea3bfeb2117e)
Change-Id: Iea61c65efb04da9cd0bc0bd85a34fc10912ea87b
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
It turned out that the `--memory-size` given at install time is
not persistent. All later anita runs use an arch-dependent default
(32M for i386, so this might explain why it was never stable).
Assuming most machines have >1GiB RAM per processor core available,
we can also increase the runtime size further (better to waste some
RAM than to wait very long because it starts swapping things out).
We choose 512MiB for 64-bit targets and 256MiB for 32-bit ones.
However, we don't need that much for the initial installation step
and it also decides the size of the swap partition. So we use a
smaller size initially that's just enough to get us through the
installation quickly enough (192MiB & 128MiB).
Change-Id: I255c41aeb92cda29ed23a236017472982e839530
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There is no disk label `a` on non-x86 (at least not on Sparc64).
Instead, we use the whole disk which is `d` on x86 and `c` else-
where. `newfs` and `fsck` needs a little help in this scenario.
Change-Id: Ib298d9cbf5d49ff38a898f4ce3ad54bb6af98d86
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The anita-based NetBSD targets need noisy, per-target handling.
Factor it out into another Makefile.
Change-Id: I0a3ca751b42f1ca8c05d93eb9740bb0ee5cc6d09
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/52483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It needs more disk space and RAM. Also, make it the default as
NetBSD 7.1 packages are gone.
Change-Id: Ic823cd30228f15859462844eb50d213487f74873
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51481
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
NetBSD 7.1 mirrors have dropped its packages, so we need something
new and more flexibility. As we have always used NetBSD 7.1 so far,
prepend the tags with `7.1-`.
To avoid re-building old images, one can re-tag them, e.g.:
$ docker image tag mani/anita:amd64 mani/anita:7.1-amd64
Change-Id: I44351805abab93c666d1d12c2bb17380caa75cec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Also add two new make targets `1.0.x` and `show-1.0.x`.
Change-Id: I2bc2e79729016a8f9908f316b051deeb73dc096f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30418
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a set of Dockerfiles for build testing. If you have an x86 machine
and ~20GiB free disk space, run `make register` and `make -jxx` in
util/manibuilder and go eat some pizza. The former runs a privileged
docker container to set binfmt_misc up for qemu (read the code, don't
trust it).
Regarding the build targets, this is the original state of Manibuilder
as it was used to build-test `flashrom-1.0`. Some fixes to the frame-
work were applied, but fixups for the targets will be done in separate
patches to maintain their original state for reference.
Change-Id: I60863a5c7d70dde71486fccb66cb59b30ba4d982
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/23005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Since interrupting the test process may be dangerous (leaving the flash
in an inconsistent state), we'll catch SIGINT and print a warning the
first time, also using it as a signal that we should stop at a
convenient time. Any following SIGINT will be handled as normal (killing
the process).
BUG=b:143251344
TEST=Run tool and verify it exits after a test with a single ^C, exits
immediately given two.
BRANCH=None
Original-Cq-Depend: chromium:2059548
Original-Change-Id: Ib8a7799cba6dbca57dc7f1d3c87521f132c21818
Original-Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2050050
Original-Tested-by: Edward O'Callaghan <quasisec@chromium.org>
Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Change-Id: If43aea0580fcc7e698daad2ffe085a3c9da5bc41
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/49915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
If the tags are missing the version may not be evaluated correctly.
BUG=b:177691209
BRANCH=none
TEST=none
Change-Id: Ib9f85b2be8b6f5e1332ba98a8a71fcad12331818
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/49618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The following is a E2E tester for a specific chip/chipset
combo. The tester itself is completely self-contained and
allows the user to specify which tests they wish to preform.
Supported tests include:
- chip-name
- read
- write
- erase
- wp-locking
Change-Id: Ic2905a76cad90b1546b9328d668bf8abbf8aed44
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This modifies CB:23025 further to work with upstream as it is now,
without the syntax changes in the patch chain. I also gave it a new
name since this script is, well, uber.
Since flashrom currently only supports reading/writing ROM-sized files
we can't easily determine a targeted region offset and size except
when a layout file is used. Therefore, some extra arithmetic is needed
in the partial write test and the only modes allowed are clobber mode
and layout mode.
A few other changes:
- Update paths and script name
- Remove write-protect testing support
- Use ROM-sized files only, no region-sized files
- Return error if flashmap or ifd mode are used
Documentation is ported from https://goo.gl/3jNoL7 into a markdown
file and accompanying SVGs. Minor changes were made for clarity and
formatting, and references to write protect testing have been removed
for the time being.
Tested using a Raspberry Pi with a W25Q16
Change-Id: I1af55d5088c54ee33853009797adbd535a506b49
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Add `util/getversion.sh` that retrieves version information from a
`versioninfo.inc` (what we use for releases) if present or uses
`util/getrevision.sh` if not.
Let Meson use it for flashrom's version. It seems Meson doesn't
generate the manual page at all, so the `--man-date` command is
currently unused.
Change-Id: I401e5638509c4a573bc0cb17ebc5fa76df9700b5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Limonciello <superm1@gmail.com>
Reviewed-by: Richard Hughes <hughsient@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enforce the DCO. The logic comes from coreboot's commit-msg hook,
and I've added a pointer to flashrom's development guidelines.
Change-Id: Iea49a06c2d4824be073eff98c8aae1cbc5b145e4
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
When compiling, this warning gives string literals the type const char[]
to help catch accidental modification (which is undefined behaviour).
There currently aren't any instances of this in flashrom, so let's
enable this warning to keep it that way. This requires adding const
qualifiers to the declarations of several variables that work with
string literals.
Change-Id: I62d9bc194938a0c9a0e4cdff7ced8ea2e14cc1bc
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Only minor differences in the Firmware Descriptor, compared to their
predecessors.
We extend our check on the `ICCRIBA` field in the descriptor to dis-
tinguish it from older generation. Alas, the `freq_read` field was
repurposed, so we can't use it as sanity check any more.
Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
It's almost identical to 100 series PCHs and later. There are some
additional FREGs (12..15). To not clutter the `if` conditions further,
make more use of `switch` statements.
Tested on Kontron mAL10. Mark it as DEP as usually the last sector
is not covered by the descriptor layout and can't be read.
Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The fwupd project has to build in all kinds of crazy targets, e.g. for odd
endians, odd instruction sets, and in odd ways, e.g. installing with a prefix
of /app for projects like flatpak. We also have other "robustness" guarantees
and therefore have a comprehensive set of CI tests which enable a lot of
warning flags and run linting and static analysis code like Coverity.
Rather than hack the Makefile I ported the codebase to use Meson.
Meson is a(nother) next-generation build system used by a lot of open source
projects ranging from low level libraries to desktop software. As part of the
port, I also copied the CONFIG_ logic from the makefile, e.g.
Option Current Value Possible Values Description
------ ------------- --------------- -----------
config_atahpt false [true, false] Highpoint (HPT) ATA/RAID controllers
config_atapromise false [true, false] Promise ATA controller
config_atavia true [true, false] VIA VT6421A LPC memory
...
At the moment I'm using the meson port so I can include flashrom as a subproject
to fwupd as distros are not yet shipping libflashrom as a shared library.
Change-Id: I3d950ece2a0568c09985eab47ddab9df1d0c43a2
Signed-off-by: Richard Hughes <richard@hughsie.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/31248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Hopefully also for other non-XP Windows build environments.
Change-Id: I7f856dc4847c4ca9197b1935b7a9b9071b46c70a
Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com>
Reviewed-on: https://review.coreboot.org/23865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There are older versions of git-rev-parse that don't understand the
`--git-path` switch. Also, when the install script was written, git-
rev-parse had a bug when it wasn't run from the root directory. They
fixed the behaviour by now. To simplify things and not have to account
for that too, we just bail out when the script is run from a sub-
directory.
Change-Id: I7ee8d4d54db48f7207fe8abf895c7fbba7685ad2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
TARGET_OS as well as EXEC_SUFFIX were only set when called via the
main makefile and even then __USE_MINGW_ANSI_STDIO was not set
for MinGW.
While at it, also replace the hardcoded gnu_printf printf format
attribute with __MINGW_PRINTF_FORMAT which is set according to
__USE_MINGW_ANSI_STDIO respectively.
Change-Id: Id146f5ba06a0e510397c6f32a2bd7c819a405a25
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/21838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
refine the pre-push hook:
- get rid of the concept of precious brances - all of them on the
upstream repos are precious (this is a change in the face of
using gerrit instead of a native git repository for staging purposes)
- likewise, only allow new versioned stable branches and no feature
branches there
Change-Id: I1d4b4a7ef2673cabee980ec4a7d7d5fbebdcaed1
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/21834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
- update the commit-msg hook to the latest one provided by Gerrit.
However, disable the (new) code that would avoid adding Change-IDs
to fixup/squash commits as needed on the staging branch
Change-Id: I2f2d7ae58dcd7d3e55959e18fe664df10bc3cc41
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/21832
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- wrap a line in the hook installer. The line still exceeds our
maximum limit by two chars but it makes no sense to break
apart the one long argument IMHO
Change-Id: I0e931fbb5902d2714d5399c1d1bfac0de35523bb
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/21831
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
