STANDALONE mode was used to build flashrom without having support for
file handling. This was relevant to build libflashrom on top of
libpayload. For a while now, the code which is covered by STANDALONE has
moved to cli_*.c and is not used for libflashrom. Therefore we can drop
STANDALONE mode.
Change-Id: I58fb82270a9884a323d9850176708d230fdc5165
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The NEED_PCI macro is only used to guard prototypes. This is not needed.
Change-Id: I6895b795bc96b3e251700bff4b0054407aac789a
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The libpci header is neither directly nor indirectly included in
flashrom.c. `PCILIB_VERSION` is therefore never set and the following
print statement is dead code. Since libpci is the only library in
buildinfo, Drop it.
Change-Id: I0b5dbf3bd82a2ffe64b73881383e92f7dad4c382
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This eliminates the need to redefine the rdmsr and wrmsr symbols,
resulting in more understandable code. The common prefix clarify the
relation between the functions.
Change-Id: Ie5ad54d198312578e0a1ee719eec67b37d2bf6a4
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add functions like
`uint32_t read_le32(const void *base, size_t offset);`
Read a 32 bit unsigned from a base with an offset.
Having prototypes and a macro generated implementation makes it easier
to read, understand and spot errors in one of them.
Change-Id: Idde177acf8bc5f94cd046b6539dc31532c98e452
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/31016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A `const` on the parameter itself is irrelevant to the caller.
Change-Id: Iea26d75719ebb718203dbba883ac88f459c68c0a
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63585
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following do-block is quite error prone to do manually,
```
io_mock_register(&XXX_io);
run_probe_lifecycle(state, &XXX, "", "..");
io_mock_register(NULL);
```.
Hence, deduce out the common pattern and fold up into the common
worker function to handle state machine setup and teardown in a
consistent way.
BUG=b:227521116
TEST=`ninja test`.
Change-Id: Icc00acd980a027337acb079f5afc3cccdfe4c765
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Daniel Campello <campello@chromium.org>
Sabrina SoC uses SMBUS revision code 0x71 which behaves exactly as the
promontory chip. Hence add 0x71 as promontory.
BUG=b:228238107
TEST=Build and deploy flashrom in Skyrim. Ensure that flashrom is able
to detect the SPI ROM chip, read from it and write to it successfully.
Ran flashrom_tester on Skyrim (Sabrina SoC) successfully and ensured
that all the tests passed.
Change-Id: I2408959fbf1c105508f0a12f38418c9606280ab9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Starting to move the platform dependent code to platform/ and provide
the abstraction through the platform.h header.
Change-Id: I35640282d451960f2a329ae24339ec05dbae6d30
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Split the code for endian conversion into separate files for big and
little endian. The buildsystem selects the correct file for the used
endianness. Replace the swab macros with `static inline` c functions.
Define macros for returning the same or swapped value. Call those macros
in the endian specific files.
Change-Id: I86d38d816b37c283279c485fac8027f8fb94364a
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On AMD SoCs that use SPI100 engine, flashrom has been using legacy
spi100 register and bit mappings when programming the engine -
specifically when programming the opcode and triggering their execution.
---------------------------------------------------------------------
| Register Name | Legacy SPI100 mapping | Updated SPI100 mapping |
|---------------|------------------------|--------------------------|
| Opcode | Offset 0 from SPI BAR | Offset 0x45 from SPI BAR |
| | Bits 0:7 | Bits 0:7 |
|---------------|------------------------|--------------------------|
| Execute Cmd | Offset 2 from SPI BAR | Offset 0x47 from SPI BAR |
| | Bit 1 | Bit 7 |
---------------------------------------------------------------------
These legacy register mappings are removed in upcoming generations of
AMD SoCs. Stop using the legacy spi100 registers. For more details about
SPI100 refer to document: 56569-A1 Rev 3.01
BUG=b:228238107
TEST=Build and deploy flashrom in Skyrim. Ensure that flashrom is able
to detect the SPI ROM chip, read from it and write to it successfully.
Ran flashrom_tester on Dewatt (Cezanne SoC), Dalboz (Picasso SoC)
successfully and ensured that all the tests passed.
Change-Id: If42130757331f4294b5a42c848557d3287f24fc3
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Unsigned types show undefined behaviour if they are subtracted by a
value greater than their own (mostly it wraps to the max value). Using
this value for left shifting could be even more dangerous.
Change-Id: I5921cc571f3dca5188ca1973dba6ececbcbe2f39
Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
For MACH / APPLE map_physical is defined in DirectHW.h
TEST: run `make`
compiles,
linking fails due to missing directhw object in my setup, don't know
how to fix this
Change-Id: I0e0f3fd587ae46e6f73418f2c83641cb1202478c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
With this change the wrappers for mock and friends are able to take an
optional io_mock_fallback_open_state struct to assert expected pathnames
and flags whenever an open operation is called.
Based partially on https://review.coreboot.org/c/flashrom/+/62319/5
BUG=b:227404721,b:217629892,b:215255210
TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom
BRANCH=none
Signed-off-by: Daniel Campello <campello@chromium.org>
Co-Author: Edward O'Callaghan <quasisec@google.com>
Change-Id: Ib46ca5b854c8453ec02ae09f3151cd4d25f988eb
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
With this change the mocks are able to return a non-negative value for
the file descriptor expected from open operations. This avoid issues
with subsequent error checks of the form `if (fd < 0)`
BUG=b:227404721
TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom
BRANCH=none
Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: Ib6bac051852aea2465665a6fd669b7f5e3772985
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This is a follow up on commit 12dbc4e04508aecfff53ad95b6f68865da1b4f07.
Use a lookup table in get_wp_mode() and drop the srp_bit_present check,
since a chip without SRP is just FLASHROM_WP_MODE_DISABLED.
Add a srp_bit_present check to set_wp_mode() if the mode requires it.
BUG=b:182223106
BRANCH=none
TEST=flashrom --wp-{enable,disable,status} on AMD dut
Change-Id: Ib6c347453f9216e5816e4ed35bf9783fd3c720e0
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit adds a generic framework to allow opaque programmers to
implement writeprotect operations and uses the framework to support
writeprotect operations on linux MTD device files.
The generic framework comprises three new functions in
`struct opaque_master` that are called from libflashrom:
- wp_write_cfg()
- wp_read_cfg()
- wp_get_ranges()
For linux_mtd, only the read/write functions are implemented. Linux's
MTD interface doesn't provide a way to get available ranges, so calling
get_wp_ranges() on the linux_mtd master will return
FLASHROM_WP_ERR_RANGE_LIST_UNAVAILABLE.
BUG=b:182223106
BRANCH=none
TEST=WP ops on hana DUT (MT8173) with W25Q32DW flash
TEST=flashrom --wp-enable --wp-range <non-empty> succeeds
TEST=flashrom --wp-enable --wp-range <empty> fails as expected
TEST=flashrom --wp-disable --wp-range <empty> succeeds
TEST=flashrom --wp-disable --wp-range <non-empty> fails as expected
TEST=flashrom --wp-status succeeds
Change-Id: I5c86e28cdec44bec49ba1d36f8ab62241b9b01da
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Chips I had available for testing were tested with all writeprotect
commands and an FT232H adapter. Chips I wasn't able to test were just
checked against the datasheets.
Chips used for testing (including chips added in previous patches) are
listed in the table below:
Flashrom Chip name | Chip(s) tested
---------------------------------+----------------------------
AT25SL128A |
EN25QH128 |
GD25LQ128C/GD25LQ128D/GD25LQ128E | GD25LQ128DSIG
GD25LQ64(B) | GD25LQ64CWIG
GD25Q127C/GD25Q128C | GD25Q127CSIG, GD25Q128ESIG
GD25Q256D | GD25Q256DYIG
GD25Q64(B) | GD25Q64CSIG
W25Q128.JW.DTR |
W25Q128.V..M |
W25Q128.W |
W25Q256JV_M |
W25Q256.V |
W25Q64.W |
XM25QH128C |
XM25QH256C |
BUG=b:182223106
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status}
Change-Id: I7f3d4c4148056098a845b5c64308b0333ebda395
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62214
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ensure the g_has_dmi_support variable has the default state
of false after the life-time has expired.
BUG=none
TEST=builds
Change-Id: I0674950304736e53d014117d287682a4f6349879
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This allows has_dmi_support to be become static local
to just the scope of dmi.c
BUG=none
TEST=builds
Change-Id: Ibded9714998ea6f2e5d4e0512fa7c6b105f9638a
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Delete the spi_read_status_register() function because the generic
spi_read_register() function can be used instead.
This patch also converts all call sites over to spi_read_register().
A side effect is that error codes are now properly propagated and
checked.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom -{r,w,E}
TEST=Tested with a W25Q128.W flash on a kasumi (AMD) dut.
Read SR1/SR2 with --wp-status and activated various WP ranges
that toggled bits in both SR1 and SR2.
Change-Id: I146b4b5439872e66c5d33e156451a729d248c7da
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Creating the entire SPI command that should be sent to the chip in
spi_write_register() is simpler than splitting it across two functions
that have to pass multiple parameters between them.
Additionally, having separate spi_write_register_flag() function
provided little benefit, as it was only ever called from
spi_write_register().
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom -{r,w,E}
TEST=Tested with a W25Q128.W flash on a kasumi (AMD) dut.
Read SR1/SR2 with --wp-status and activated various WP ranges
that toggled bits in both SR1 and SR2.
Change-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59528
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds Meteor Lake support into flashrom.
Additionally, utilize CSSO (CPU Soft Strap Offset) to uniquely detect
the chipset when the CSSL (CPU Soft Strap Length) field default value
(0x03) on Meteor Lake is the same as Elkhart Lake.
BUG=b:224325352
TEST=Flashrom is able to detect MTL SPI DID and show chipset name as below:
> flashrom --flash-name
....
Found chipset "Intel Meteor Lake-P/M".
....
> flashrom - internal --ifd -i fd -i bios -r /tmp/bios.rom
....
Reading ich_descriptor... done.
Assuming chipset 'Meteor Lake'.
Using regions: "bios", "fd".
Reading flash... done.
SUCCESS
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0a2ffe2ba8d96c90d89b77e0d8583d179ff02a75
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sam McNally <sammc@google.com>
In function flash_layout_read_from_ifd variable chip_layout remains
uninitialized if prepare_flash_access returns false. This uninitialized
variable (which contains a garbage value) is passed to
flashrom_layout_release. Thus initialize it with NULL. For completeness,
also initialize dump_layout with NULL.
Change-Id: Iacbd7bf9cdf897cc2a732c1dc6568845a4ab804d
Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62725
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In function board_asus_p3b_f there were two consecutive lines which
modified the value of variable b
// Do something with b
b=INB(0x80);
b=INB(smbba);
//Do something with b
Since the value of b is not used after first assignment, remove the
first assignment.
Change-Id: I7458b416a69fd5e2aa300ca49d1352b6074ad0bc
Tested-by: Keith Hui <buurin@gmail.com>
Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This programmer operates much the same as realtek_mst_i2c_spi, so the
I2C options are moved to a new section describing both programmers
and a short description is added for this programmer itself.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I9ccb9694fdea29e68f062cc049efc0204917a139
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
This programmer was undocumented.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Idde5a8de014fe84c4a472f8fbfd3562350997d39
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
This change adds follow up changes to the man page:
- Explain (-) argument for -w/-v operations
- Expand on region name handling of -x operation
Also updates cli_classic.c to match with --help output.
BUG=b:224364316
Change-Id: I0cba593da3926c8587027789f4e1e89a2329ca7f
Signed-off-by: Daniel Campello <campello@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The issue was found by running scan-build. Memory leak was caused as
data variable wasn't deallocated in some error cases where the
function returned without deallocating it. After making the change, the
issue no longer appeared in scan-build.
Change-Id: I7910db94f63693e7f131836d4963e88cfdbec301
Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This change addresses the following ASAN error detected in the chromium
tree:
* ASAN error detected:
* ../flashrom-9999/helpers.c:28:13: runtime error: left shift of 1 by 31 places cannot be represented in type 'int'
* #0 0x5589a94bb284 in address_to_bits /build/amd64-generic/tmp/portage/sys-apps/flashrom-9999/work/flashrom-9999-build/../flashrom-9999/helpers.c:28:13
*
* SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../flashrom-9999/helpers.c:28:13 in
BUG=b:224828279
TEST=./test_build.sh; FEATURES=test emerge-amd64-generic flashrom
BRANCH=none
Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: Ib595f13c29dd5c0775e074801756e4f920b4daaf
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62862
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change allows for tests to run when the compiler is inlining some
other interfaces. This happens when compiling on the chromium chroot
environment.
* __fgets_chk() is being used instead of fgets() in
get_max_kernel_buf_size() on linux_spi.c
* __vfprintf_chk() is being used instead of fprintf() in
disable_power_management() on power.c
* __open64_2() is being used instead of open() in i2c_open_path() on
i2c_helper_linux.c
BUG=b:224828279
TEST=./test_build.sh; FEATURES=test emerge-volteer flashrom
Signed-off-by: Daniel Campello <campello@chromium.org>
Change-Id: I9776104d655c37891093da08789d37e5e27700de
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This test adds a mock for linux_spi ioctl and mocks it for read
request. Read buffer is populated with chip manufacture id and
chip model id to emulate successful probing.
BUG=b:181803212
TEST=ninja test
Change-Id: I32d8e972d99b52c2b18f688aa6aeae75dd170f72
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
No additional mocks are needed, because linux_mtd is doing most of
the job in init function.
BUG=b:181803212
TEST=ninja test
Change-Id: I74436f36f628680c22c7225b1584f06464307775
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Thomas Heijligen <src@posteo.de>
This patch implements run_probe_lifecycle and adds dummyflasher
test to run probing lifecycle.
A lifecycle consists of 3 steps: 1) init programmer 2) do some action
3) shutdown programmer. Step 2 can be "do nothing", and this is
named "basic lifecycle", i.e. the simplest. This patch implements
"probe lifecycle" which probes a chip as Step 2.
Internally there is one run_lifecycle function which performs steps
1, 2, 3. run_lifecycle is operating via libflashrom API. Long term
goal for cli_classic is to operate via libflashrom API, so the test
aligns with this approach.
BUG=b:181803212
TEST=ninja test
Change-Id: I9eb7fe3a436fbba5e70db957139fd26e00efec36
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Align the usage of serial function with the selection of other
dependencies.
Change-Id: Ica951e76d6362b01f09d23a729a2a6049e7f0b66
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Abstract the different I/O Port permission methods in own functions.
Change-Id: If4b2f8c2532f3732086ee1d479da6ae6693f9a42
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/61275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
