As per Tomasz Walach on the mailing list.
Change-Id: Ib0d7485c7221f92ec13995c58065a48e08f57cd8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As per Stefan Szwarnowski on the mailing list.
Change-Id: I574094bdb83611a3cda2fcc455bcf9aed3774011
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As per Richard Hughes via the mailing list.
Change-Id: Ic562a65d1a7d394f9d2c3980833d10a87bd9358a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As per Konstantin on 2018-06-08 via mailing list.
Change-Id: I75fb4b17cf330451489811ae9303cbb33ebcb183
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As reported by David Martinka on the mailing list.
Erase has not been tested, but since writes are reported as working, it
is very likely erase works as well.
Change-Id: I172453fe902ccface2a3a85817d775d45dd7cf80
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Alexander reported this chip as tested using a GD25B128CPIG (same device
ID, apparently) on 2018-08-30 via the mailing list. The chip name is
updated as well.
Change-Id: I134d3816c0f02e20764ab132a01bcba9f4e93f0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Grabbed from mailing list, created by Simon Buhrow. Since no logs were
attached, the chip is marked as untested.
Change-Id: Idc26162fc5a5a429acef546b30b12d8b1f195e0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Copy 'n paste support for Macronix MX25U51245G. I don't pretend to know
a whole lot about SPI FLASH so its mostly copied from other MX25U devices
and double checked a few bits and pieces against the datasheet.
I have tested basic probe, read, erase and write using layout files. I
tested both with 4MB@0x0000000 and 64K0@0x3f00000 (the later means I
have tested 4-byte addressing).
Change-Id: I2117fc205006088967f3d97644375d10db1791f1
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Reviewed-on: https://review.coreboot.org/26949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is the low-voltage version of the AT25DF021. Tested with FT2232H
Mini Module
Change-Id: If4990e6856c8b77567ef4218459cf754b9c6bc57
Signed-off-by: Steffen Mauch <steffen.mauch@gmail.com>
Reviewed-on: https://review.coreboot.org/26856
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Same story as for 25Q80BW/EW, 25Q40EW has a new ID and the only known
chip with the old ID is the BW variant.
Change-Id: Ib610b0d6f3a5561b2ac3505ef15bdee8b0edae25
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/25462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This patch seems to have originally been from
https://patchwork.coreboot.org/patch/4126/ . The most recent version
seems to be in OpenEmbedded (commit 503a572) which added support for
16Mbit and 32Mbit variants.
The OpenEmbedded patch also makes changes to linux_spi.c to add some
debug prints which are omitted in this version.
From the original commit message:
Differences between SST26 and SST25:
1. The WREN instruction must be executed prior to WRSR [Section 5.31].
There is no EWSR.
2. Block protection bits are no longer in the status register. There
is a dedicated 144-bit register [Table 5-6]. The device is
write-protected by default. A Global Block-Protection Unlock
command unlocks the entire memory [Section 4.1].
Change-Id: Ib019bed8ce955049703eb3376c32a83ef607c219
Signed-off-by: Wei Hu <wei@aristanetworks.com>
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Reviewed-on: https://review.coreboot.org/25962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The W25Q80BW appears to have been succeeded by the W25Q80EW which has a
different manufacturer ID but is otherwise similar. Consequently, W25Q80.W
no longer matches all chips in this family.
This patch makes the original entry specific to W25Q80BW.
Change-Id: I2980272c2691eb62a68056a7a4c308e9b4810347
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This introduces the Zettadevice manufacturer ID and adds support for the
ZD25D40 chip.
Based on PR20 from Github.
Change-Id: I0400b059ddacdf166d1b77f619becec3a250cece
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/23701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This adds support for W25P80/16/32 chips. Most notably these chips only
have two erase commands - one for 64KiB "sectors" and one for chip
erase.
Change-Id: Ie09ba8e28fee35c42e17ca05219dc673413de93b
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/23700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ENE Embedded Debug Interface (EDI) is a SPI-based interface for
accessing the memory of ENE embedded controllers.
The ENE KB9012 EC is an embedded controller found on various laptops
such as the Lenovo G505s. It features a 8051 microcontroller and
has 128 KiB of internal storage for program data.
EDI can be accessed on the KB9012 through pins 59-62 (CS-CLK-MOSI-MISO)
when flash direct access is not in use. Some firmwares disable EDI at runtime
so it might be necessary to ground pin 42 to reset the 8051 microcontroller
before accessing the KB9012 via EDI.
The example of flashing KB9012 at Lenovo G505S laptop could be found here:
http://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate
Change-Id: Ib8b2eb2feeef5c337d725d15ebf994a299897854
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/23259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Advertise all 4BA features that are currently supported by flashrom,
plus add a new feature flag for the 4BA fast-read instruction. Also,
list all supported 3BA and 4BA erase-block functions.
As this adds a lot of new code paths that could be taken for these
chips, mark them all as untested again.
Change-Id: I0598496ee7058e3b170684d366f58e4014e0e871
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22423
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Instead of arbitrarily deciding whether to enter 4BA mode in the flash
chip's declaration, advertise that entering 4BA mode is supported and
only enter it if the SPI master supports 4-byte addresses. If not, exit
4BA mode (the chip might be in 4BA mode after reset). If we can't assure
the state of 4BA mode, we bail out to simplify the code (we'd have to
ensure that we don't run any instructions that can usually be switched
to 4BA mode otherwise).
Two new feature flags are introduced:
* FEATURE_4BA_ENTER:
Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN.
* FEATURE_4BA_ENTER_WREN
Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN.
FEATURE_4BA_SUPPORT is dropped, it's completely implicit now.
Also, draw the with/without WREN distinction into the enter/exit
functions to reduce code redundancy.
Change-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22422
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Prefer the native 4BA instruction when they are supported. In this
case, override our logic to decide to use a 4BA address.
Change-Id: I2f6817ca198bf923671a7aa67e956e5477d71848
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22385
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IS25LP128 is the 3.3V variant, IS25WP128 is the 1.8V variant.
Tested read, erase, and write using Dediprog SF600 on each.
Change-Id: Ia1c7a9a950043c30b7525196e03ee394689e89a5
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/22784
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Just another chip sharing the same ID. Tested by somebody on IRC.
Change-Id: Ibea956e48e10fda91930b65b3bf3b3ae4ad13f63
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This allows us to support flash chips in any of the following
configurations, regardless of whether the chip powers up in 3-byte or
4-byte address mode.
- standard commands with extended address register (*_4ba_ereg) or
direct commands (*_4ba_direct) in 3-byte address mode (.set_4ba =
spi_exit_4ba_*)
- standard commands (*_4ba) or direct commands (*_4ba_direct) in
4-byte address mode (.set_4ba = spi_enter_4ba_*)
- direct commands (*_4ba_direct) in either address mode (.set_4ba =
NULL)
Change-Id: I0b25309d731426940fc50956b744b681ab599e87
Signed-off-by: Ed Swierk <eswierk@skyportsystems.com>
Reviewed-on: https://review.coreboot.org/20510
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Large flash chips usually support special instructions to work with
4-bytes address directly from 3-bytes addressing mode and without
do switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program)
and 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these
instructions are supported by all large flash chips. Some chips
support 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends
on the manufacturer of the chip.
This patch provides code to use direct 4-bytes addressing instructions.
This code should work but it tested partially only. My W25Q256FV has
support for 4BA_Read (13h), but doesn't have support 4BA_Program (12h)
and 4BA_Erase instructions. So, direct 4BA program and erase
should be tested after.
Patched files
-------------
chipdrivers.h
+ added functions declarations for spi4ba.c
flash.h
+ feature definitions added
flashchips.c
+ modified definition of Winbond W25Q256BV/W25Q256FV chips
flashrom.c
+ modified switch to 4-bytes addressing for direct-4BA instructions
spi4ba.h
+ definitions for 4-bytes addressing JEDEC commands
+ functions declarations from spi4ba.c (same as in chipdrivers.h, just to see)
spi4ba.c
+ functions for read/write/erase directly with 4-bytes address (from any mode)
Change-Id: Ib51bcc5de7826b30ad697fcbb9a5152bde2c2ac9
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013198.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20508
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Here is the definition of new W25Q256xV chip with new functions pointers
for 4-bytes addressing reads and writes. Erase functions pointers are
changed in their old places. New feature flags for 4-bytes mode added.
Patched files
-------------
flashchips.c
+ added definition for Winbond W25Q256BV/W25Q256FV chips
Change-Id: I90226f453f8147ae5ac7dbbef7549ee3bfacc3d6
Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014
[clg: ported from
https://www.flashrom.org/pipermail/flashrom/2015-January/013201.html ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-on: https://review.coreboot.org/20506
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only difference to its sibling W25Q128.V seems to be the supply voltage.
Change-Id: I34ce7f1bdd0d2fb1b065031e5a689bb16ffc70db
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested mainboards:
OK:
- ASRock Fatal1ty 970 Performance and P4i65G
Reported by anonymous email message ID:
932677687262b1300eaf14260999d9262c31@guerrillamail.com
The latter actually had a tested board enable already.
Flash chips:
- Eon EN25Q128 to PREW (+PREW)
Reported by Adrian Graham
- GigaDevice GD25VQ41B to PREW (+PREW)
Reported by David Hendricks
- Winbond W39V040FB to PREW (+EW)
Reported by fjed on IRC
Miscellaneous:
- Change PCI IDs of "MS-6577 (Xenon)" board enable.
The previous IDs contained the on-board display adapter which is
disabled when a dedicated graphics card is installed.
- Add a note to the README how to overcome the clang warning if only a
single programmer is enabled.
- Fix some typo and manpage problems found by lintian
- r1920 introduced some explicit calls to pkg-config instead of $(PKG_CONFIG).
This patch corrects that.
- Make MS-7094 (K8T Neo2-F V2.0) board enable less contestable.
Previous PCI IDs were board-specific but ot the other of devices
that could be disabled by the firmware or that vary among
hardware revions. There are no good alternatives available.
However, since we always have a DMI decoder available now, we can
use non-board-specific devices without taking risks. Thanks to
Uwe Hermann for reporting and testing.
- Some other small changes to clean up whitespace and fix some warnings
from Debian's lintian.
Corresponding to flashrom svn r1951.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The earlier versions of the chip require 0x2AAA for probes thus split the
definitions and set them to untested to provoke reports.
Corresponding to flashrom svn r1922.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested mainboards:
OK:
- ASRock G31M-GS
Reported by Александр Трубицын
- ASRock G41M-VS3
Reported by Александр Трубицын
- ASRock N68C-S UCC
Reported by Alexey Belyaev
- ASRock AMCP7AION-HT (ION 330HT(-BD))
Reported by Stefan Tauner
- ASUS P5K SE
Reported by Александр Трубицын
- ASUS P5KPL-VM
Reported by Marin Vlah
- ASUS RAMPAGE III GENE
Reported by stevessss on IRC
- GIGABYTE GA-945GM-S2
Reported by Александр Трубицын
- GIGABYTE GA-945GCM-S2 (rev. 3.0)
Reported by Александр Трубицын
- GIGABYTE GA-965P-S3
Reported by Александр Трубицын
- GIGABYTE GA-EG43M-S2H
Reported by Александр Трубицын
- GIGABYTE GA-EP31-DS3L (rev. 1.0)
Reported by Александр Трубицын
- GIGABYTE GA-G33M-S2
Reported by Александр Трубицын
- GIGABYTE GA-G33M-S2L
Reported by Александр Трубицын
- GIGABYTE GA-H55M-S2
Reported by Александр Трубицын
- GIGABYTE GA-J1900N-D3V
Reported by Marcos Truchado and Guillermo von Hünefeld
- GIGABYTE GA-K8NS
Reported by nicolae788
- GIGABYTE GA-M56S-S3
Reported by Estevo Paz Freire
- GIGABYTE GA-P31-DS3L
Reported by Александр Трубицын
- GIGABYTE GA-P31-S3G
Reported by Александр Трубицын
- MSI MS-7336
Reported by Benjamin Bellec
- MSI X79A-GD45 (8D) (MS-7760)"
Reported by mortehu on IRC
- Supermicro A1SAi-2550F
Reported by Bernard Grymonpon
- Supermicro X7DWT
Reported by Steven Stremciuc
Laptop:
- ASUS U38N
Reported by Ultra on IRC
- Dell Latitude D630
Reported by Márton Miklós
- Fujitsu Amilo Xi 3650
Reported by Elmar Stellnberger
- Lenovo T400 (whitelisting only)
Chipsets:
- Mark 8086:1f38 (Intel Avoton/Rangeley) as tested
Reported by Jeremy Porter and Bernard Grymonpon
- Add Intel Sunrise Point IDs but no support yet.
Flash chips:
- Atmel AT45DB321D to PREW (+PREW)
Reported by The Raven
- Eon EN25QH32 to PREW (+PREW)
Reported by Josua Mayer
- Eon EN25QH64 to PREW (+EW)
Reported by David s. Alessio
- GigaDevice GD25LQ64(B) to PREW (+PREW)
Reported by Greg Tippit
- Intel 28F001BN/BX-T to PREW (+EW)
Reported by Lu Xie
- Micron M25P10-A to PREW (+W)
Reported by the Raven
- Micron M25PE40
Reported by David Wood
- Micron N25Q128..3E to PREW (+PREW)
Reported by Miklós Márton
- Macronix MX25L3273E to PREW (+PREW)
Reported by Roklobsta on IRC
- Macronix MX23L6454 to PR (+PR)
Reported by Steven Honeyman
- Macronix MX25U6435E/F to PREW (+PREW)
Reported by Marcos Truchado and Guillermo von Hünefeld
- PMC Pm25LQ032C to PREW (+EW)
Reported by Dirk Knop
- Spansion S25FL016A to PREW (+EW)
Reported by Márton Miklós
- Spansion S25FL128S......0 to PREW (+PREW)
Reported by Jim Houston
- Spansion S25FL204K to PR (+PR)
Reported by Thomas Debrunner
- SST SST49LF016C to PREW (+EW)
Reported by Steven Stremciuc
- SST SST39VF040 to PREW (+PREW)
Reported by Xavier Bourgeois
- SST SST49LF040B to PREW (+EW)
Reported by Rikard Åhlund
- ST M25P10-A to PREW (+W)
Reported by Martijn Schiedon
- Winbond W39V040FA to PREW (+EW)
Reported by Евгений Черкашин
- Winbond W39V080FA to PREW (+EW)
Reported by protagonist0 on IRC
- Winbond W25Q80.W to PREW (+PREW)
Reported by Miklós Márton
- Winbond W25X64 to PREW (+REW)
Reported by Johannes Krampf and Manuel Dejonghe
- Fix ID of AMIC A25LQ64
Reported by Roman Titov
- Fix page size of Spansion S25FL129P......1
Copy and paste error from the 128S uniform 256kB variant, probably.
- Add Micron/Numonyx phase-change memory IDs
Miscellaneous:
- Detect Android target OS.
No changes are required to build flashrom (excluding programmers
with NEED_PCI) on Android.
- Update rayerspi (spipgm) URL
- Fix max_data_write handling of at45db.
- Minor refinement of the README
- Mark board enable for the GA-K8NS variants as tested.
Tested by "nicolae788" on a board with socket 754.
- Mark "Multi-system" chassis as non-laptop case.
- Remove W836xx log requests.
We got enough (and no one is looking at them for the time being anyway).
- serprog: improve invalid reply error message, contributed by Urja Rannikko.
- Remove default include paths for MinGW.
- Disable implicit rules in the Makefile because we don't need them and they
just make the build (imperceptibly) slower.
- Enable our own strnlen() implementation not only on DJGPP but also if
HAVE_STRNLEN is not defined. This is needed to get older BSDs
(e.g. NetBSD 6.0, FreeBSD < 8.0) to work.
- Tiny other stuff.
Corresponding to flashrom svn r1917.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Corresponding to flashrom svn r1903.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Jose Luis León <zenky1@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Apart from the strange ID (using Sanyo's vendor ID 0x62) the main
difference from the plain SST25WF series is that they lack op codes
0xAD (AAI Word program) and 0x52 (32K erase). The smallest version
does not support dual I/O operations either.
SST25WF080B was tested under Linux with spidev.
Corresponding to flashrom svn r1901.
Tested-by: Ben Gardner <bgardner@wabtec.com>
Signed-off-by: Ben Gardner <bgardner@wabtec.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
