Turns out CONFIG_RAIDEN was missing in the LIBUSB1
as no overrides. Credit to HAOUAS Elyes for spotting this.
Change-Id: I7dd26665a0133175949c11717837e9de68a1bf71
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The raiden_debug programmer is of type USB. However, it does not set the
field `devs.dev`, which will result in a segfault when trying to print
the devices of the non-existing table.
Fix that by replacing `devs.note` with `devs.dev` and adding an empty
device table. Since Device IDs are not used to match programmers,
nothing could be added to the table.
TEST=Running `flashrom -L` no longer segfaults and returns normally.
Change-Id: Ie4171a11384c34abb102d1aadf86aa1b8829fc04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Support GD25WQ80E, which is the internal flash of IT81202.
TEST=Building flashrom and flashing FW image into IT81202 successfully.
Change-Id: Ib5feaa6ecc7b11b2218e5f02c087b4331388bef8
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
32Mbit (4MiB) [x1/x2/x4] Wide Voltage Range (VCC 1.65V-3.6V). It is
similar to the already-supported MX25R6435F, but the total size is
halved.
Tested on ch341a, FT4232H and FT2232H (PicoTAP) programmers, confirmed
working probe, read, erase and write.
Fixes: https://github.com/flashrom/flashrom/issues/43
Change-Id: I6e79115adba17d13d24bc85d78707d53fd4a0be5
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested reading, writing and erasing the internal flash chip using an
Acer Aspire ES1-572 laptop with an Intel i3-6006U. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall
follow suit as well.
Change-Id: Ib8ee9b5e811df74d2f48bd409806c72fe862bc24
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Add a delay following the AP and EC flash enable requests. This allows
any power rails enabled by these signals to settle and to meet the power
on to first SPI write timing requirements.
Forward ports the downstream commit:
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2036738
Change-Id: I4c1777777ee67580605c6e6f4c0c228cccc392c7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This overcomes a problem with the ServoMicro where USB packets can be
ack'd by the device without triggering interrupts or loading data into
the USB endpoints. The retry mechanism attempts the USB read 3 times
before reattempting the write call to avoid performing multiple SPI
transfers due to a USB problem. This process repeats 3 times before we
return the last error code. Intermediary problems are reported in the
status code.
Based off the downstream commit:
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2038271
Change-Id: I76cde68852fa4963582d57c7dcb9f24de32c6da8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- The USB SPI interface has been split up into write and read stages.
- The packet packing has been transitioned from array based to a
struct.
This was based off the downstream commit:
https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2036508
Change-Id: Id3a2a544c1c7e1d969a5157977b8a1c7af18371b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/39309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This only sets 3rd CS# bit be asserted during read/write operations.
Tested and confirmed working on 4232H & PicoTap ft2232 programmers
against MX25R6435F & S25FL128S chips.
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Change-Id: Ia0ac14b9a52f251306887500dae3e57d73322157
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This allows multiple 'csgpiol' bits to be set to active state at the
same time. Previously, only one GPIOL could be activated. I have an
use-case such that FT4232H is wired to two different SPI chips, and in
order to select one of them two GPIOLs have to be set.
Now, one can enable any particular GPIOL, for example:
csgpiol=01
would activate GPIOL0 and GPIOL1 at the same time.
The change is backward-compatible with previous csgpiol formatting.
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Change-Id: I645ddaa9852e9995bd2a6764862fda2b2ef0c26b
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Added spireadmode for >= Bolton.
Do not override speed or read mode for >= Bolton if parameter not
specified.
Minor cleanup of sb600spi.c code.
TEST=Manual: deploy on tremblye read flash using various parameters
BUG=b:147665085,b:147666328
BRANCH=master
Change-Id: Id7fec7eb87ff811148217dc56a86dca3fef122ff
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These are helpful usb device accessors and helpers that
are later used for the so-called Raiden debugger programmer.
BUG=b:143389556
BRANCH=none
TEST=builds
Change-Id: Ic928220fc919fe4958c8150e61e11470dac88f13
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The following is a E2E tester for a specific chip/chipset
combo. The tester itself is completely self-contained and
allows the user to specify which tests they wish to preform.
Supported tests include:
- chip-name
- read
- write
- erase
- wp-locking
Change-Id: Ic2905a76cad90b1546b9328d668bf8abbf8aed44
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This modifies CB:23025 further to work with upstream as it is now,
without the syntax changes in the patch chain. I also gave it a new
name since this script is, well, uber.
Since flashrom currently only supports reading/writing ROM-sized files
we can't easily determine a targeted region offset and size except
when a layout file is used. Therefore, some extra arithmetic is needed
in the partial write test and the only modes allowed are clobber mode
and layout mode.
A few other changes:
- Update paths and script name
- Remove write-protect testing support
- Use ROM-sized files only, no region-sized files
- Return error if flashmap or ifd mode are used
Documentation is ported from https://goo.gl/3jNoL7 into a markdown
file and accompanying SVGs. Minor changes were made for clarity and
formatting, and references to write protect testing have been removed
for the time being.
Tested using a Raspberry Pi with a W25Q16
Change-Id: I1af55d5088c54ee33853009797adbd535a506b49
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
As found on the Tesla AP2.5 board.
Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html
Tested with:
flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin
Signed-off-by: Bernhard Urban-Forster <lewurm@gmail.com>
Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Intel Ice Lake systems use an 495 Series Chipset
that behaves compatible to pch300 chips but chip names
are undocumented at this point.
This change was tested in read/write/erase on the Razer
Blade Stealth (late 2019) with intel 1065G7 CPU and
"Ice Lake U Premium PCH".
Change-Id: I6227d32f4476420cf1aeec37ebd4b7648e0b3d15
Signed-off-by: Johanna Schander <git@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/37987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Intel Kaby Lake U (with the 9d4e device id) support is available but
marked not tested.
Tested reading, writing and erasing both internal flash chips on the
Facebook Monolith system with the Intel i3 7100U SoC. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall follow
suit as well.
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Change-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38481
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit e28d75ed7204d7fac2c0fac13978098530b0574e.
This is broken in multiple ways, e.g. pcidev_init() can only return
NULL.
Change-Id: I06242147ba9d3a062d442f645eb0800ef51af19f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Reported-by: Michael Bishop <cleverca22@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38319
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
GCC 4.8 wants an explicit `-std=c99` or something for this to work. It
seems easier to keep the common declaration style.
Change-Id: Ic0819f82169df4d66cc949494229b0749c06e8f6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Miklós Márton <martonmiklosqdev@gmail.com>
Tested reading, writing and erasing the internal flash chip using a
Samsung NP530U3C laptop with an Intel HM76 PCH. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall
follow suit as well.
Change-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/37803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Something to point users to when SMM_BWP might be causing problems.
Change-Id: I394c033e8d4ff96433162f86aefb428d8acf6349
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit adds support for the Adesto AT25SF321 SPI flash chip. Probe
and read operations have been tested via FT2232H interface, but writes
have not been verified.
Datasheet is available at the following URL:
https://www.adestotech.com/wp-content/uploads/DS-AT25SF321_047.pdf
Change-Id: I7410815e063ffe154a97d7ea5881c8eb82025f56
Signed-off-by: Peter Adkins <pete@kernelpicnic.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Don't entagle the code paths for the two NIC classes if it's not necessary.
Only compile tested.
Change-Id: I59164ccf54afbbd64a0598282d13e80ff7fd6fa4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/33637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit 61e16e549a52194ac80ef40504f2dc661d1ff99c.
Obviously throws alignment in the table off and changes output
class from `general` to `programmer` for no visible reason.
Change-Id: I864044b9fac6af9cf6a89c053eccdcb36f17c7bd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Tin Can Tools Flyswatter and Flyswatter 2 have a FT2232H
with a JTAG interface wired to port A. The buffers that drive the
JTAG pins need to be enabled with an nOE signal from the
FT2232H ADBUS6 and ADBUS7 pins.
Flyswatter has an ARM-14 JTAG interface and Flyswatter 2 has
an ARM-20 JTAG interface.
Change-Id: I56b1fb76dcda32bb02980cd54a2853506bfc9dfd
Signed-off-by: Russ Dill <Russ.Dill@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Write a pure function for the table validation logic, it is
easier to unit-test.
Change-Id: I07b0f95ec0443fa6a8f54eb93f4a7ea1875cccad
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/37239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Write a pure function for the header validation logic, it is
easier to unit-test.
Change-Id: Ia288bcbc5c371329952a6efba30ccf0e18965a3d
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/37238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When multiple dediprog programmers are connected, the 'id' parameter
allows you to specify which one to use. The id is a string like SF012345
or DP012345. The value is printed on a sticker on the back of the dediprog.
This is an improvement over the 'device' parameter which is based on
enumeration order and changes when you plug/unplug devices or reboot the
machine.
To find the id without the sticker, run flashrom with the -V option.
This prints the ids as they are enumerated. Alternatively, with dpcmd,
you can use the --list-device-id and --fix-device commands to list and
write device ids respectively.
Note this only supports SF100 at the moment, but SF600 support is
possible with more work.
Change-Id: I4281213ab02131feb5d47bf66118a001cec0d219
Signed-off-by: Ryan O'Leary <ryanoleary@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Port the code from chromeos flashrom
BUG=b:144297264
TEST=Tested using W25Q128JWDTR in SPI mode
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/36717
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds missing voltage and capacity variants for N25Q and MT25Q
series devices. This also fixes a typo in some model numbers where the
last letter should have been a G instead of an E. Added devices include:
N25Q256..1E
N25Q512..1G
N25Q00A..1G
N25Q00A..3G
MT25QU128
MT25QL128
MT25QU256
MT25QU512 tested by Jacob Creedon <jcreedon@google.com>
MT25QL01G tested by Konstantin Grudnev <grudnevkv@gmail.com>
MT25QU01G
MT25QL02G
MT25QU02G
Two have been tested as indicated, all other variants added are marked
untested.
Signed-off-by: Jacob Creedon <jcreedon@google.com>
Change-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e
Reviewed-on: https://review.coreboot.org/c/flashrom/+/34491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Add `util/getversion.sh` that retrieves version information from a
`versioninfo.inc` (what we use for releases) if present or uses
`util/getrevision.sh` if not.
Let Meson use it for flashrom's version. It seems Meson doesn't
generate the manual page at all, so the `--man-date` command is
currently unused.
Change-Id: I401e5638509c4a573bc0cb17ebc5fa76df9700b5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Limonciello <superm1@gmail.com>
Reviewed-by: Richard Hughes <hughsient@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Introduce cli_classic_single_operation() to consolidate the repeating
pattern of multiple CLI operations at once. Also modify
cli_classic_abort_usage() to take an optional error abort string and
print it to stderr, this allows for trimming a few more lines off the
cli implementation.
V.2: A few fixes upon review:
- Trim off some unnecessary braces for single line branches.
- Pass 'operation_specified' by reference.
- Rename a function.
V.3: Fix print order of cli_classic_abort_usage().
Change-Id: I54598efdaee2b95cb278b0f2aac05f48bbd95bef
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Make the first line of --help in usage to align with the
format of the man page, including fixing any missing options.
V.2: Add an extra space.
Change-Id: I44f82c6a54fddb54bf268fe6eb22e50acb6025cf
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/35793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
