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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-28 15:33:42 +02:00
Carl-Daniel Hailfinger 15aa7c6543 Use REMS instead of RES in the ICH SPI default opcode table
RES is Read Electronic Signature (1 Byte, identical for different chips)
REMS is Read Electronic Manufacturer Signature (2 Bytes, mostly unique)
RDID is Read JEDEC ID (3 bytes, unique)

Of the chips which don't support RDID, a sizable portion supports REMS
which gives us both a manufacturer ID and a device ID. This is clearly
superior to having only a device ID (the RES case) which has multiple
documented collisions.

The RES/REMS problem is aggravated by inconsistent naming in vendor data
sheets. What's in a name? Considering that we have 1-byte IDs, 2-byte
IDs and 3+byte IDs with varying names but mostly consistent opcodes, it
makes sense to set our own standard about how the opcodes are called.

The best way forward would be to have the ICH SPI driver reprogram the
opcode menu on the fly if the opcode menu doesn't contain the requested
opcode and the opcode menu is not locked. Until that happens, this patch
improves detection accuracy by a factor of 256 for some chips.

Corresponding to flashrom svn r549.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Tested-by: Uwe Hermann
with the flash chip "SST SST25VF040.REMS".

Acked-by: Ronald G. Minnich <rminnich@gmail.com>
2009-05-26 21:25:08 +00:00
2009-05-26 09:48:28 +00:00
2009-05-26 09:48:28 +00:00
2007-09-08 14:36:01 +00:00
2009-05-25 23:26:50 +00:00
2009-05-25 23:26:50 +00:00
2009-05-17 22:57:34 +00:00
2009-05-22 13:18:38 +00:00
2009-05-17 15:49:24 +00:00
2009-05-25 23:26:50 +00:00

-------------------------------------------------------------------------------
flashrom README
-------------------------------------------------------------------------------

flashrom is a utility for reading, writing, verifying and erasing flash ROM
chips. It's often used to flash BIOS/EFI/coreboot/firmware images in-system
using a supported mainboard, but it also supports flashing of network
cards (NICs), SATA controller cards, and other external devices which can
program flash chips.

It supports a wide range of DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, and
TSOP40 chips, which use various protocols such as LPC, FWH, parallel flash,
or SPI.

(see http://coreboot.org for details on coreboot)


Build Requirements
------------------

To build flashrom you need to install the following packages or ports:

Linux et al:

 * pciutils
 * pciutils-devel / pciutils-dev / libpci-dev
 * zlib-devel / zlib1g-dev

On FreeBSD, you need the following ports:

 * devel/gmake
 * devel/libpci

To compile on Linux, use:

 make

To compile on FreeBSD, use:

 gmake

To compile on Solaris, use:

 gmake LDFLAGS="-L$pathtolibpci -lpci -lz" CC="gcc -I$pathtopciheaders" \
       CFLAGS=-O2

To compile on DragonFly BSD, use:

 ln -s /usr/pkg/include/pciutils pci
 gmake CFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -lpci -lz"

To compile and run on Darwin/Mac OS X:

 Install DirectIO from coresystems GmbH.
 DirectIO is available at http://www.coresystems.de/en/directio.


Usage / Options
---------------

Please see the flashrom(8) manpage.


Exit status
-----------

Please see the flashrom(8) manpage.


coreboot Table and Mainboard Identification
--------------------------------------------

Please see the flashrom(8) manpage.


ROM Layout Support
------------------

Please see the flashrom(8) manpage.


Supported Flash Chips / Chipsets / Mainboards
---------------------------------------------

Please check the output of 'flashrom -L' for the list of supported
flash chips, chipsets/southbridges, mainboards, and flash programmers.

Website
-------

The official flashrom website is:

  http://coreboot.org/Flashrom

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