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Commit Graph

81 Commits

Author SHA1 Message Date
b69591add3 Add support for detecting Intel CascadeLake CPUs (#271)
Should close
https://github.com/google/cpu_features/issues/260
2022-09-19 10:00:01 +02:00
4e8d2e3a22 add intel goldmont plus (#256)
* add intel goldmont plus (INTEL_ATOM_GMT_PLUS)
2022-08-08 09:27:18 +02:00
426b036e8d Added some missing amd k12 uarch (#259)
* Add comment about AMD_K12 LLANO.
* Add family 0x12 model 0x00 to it.
2022-08-04 22:30:46 +02:00
c6b0a803a8 Add AVX_VNNI 2022-08-04 21:56:32 +02:00
6d62f2fa64 add intel Tremont microarch 2022-08-04 21:54:23 +02:00
8d86a40b7a [NFC] Restrict windows inclusion to windows platforms 2022-07-28 14:24:57 +00:00
601471d527 Add detection LZCNT (#254)
Fixes #253
2022-07-28 12:22:16 +02:00
677d6419b2 remove internal FillX86BrandString usage (#258) 2022-07-25 17:39:50 +02:00
c7c7751682 Add macros for RISCV hwcaps (#246)
Co-authored-by: Michael Roe <michael-roe@users.noreply.github.com>
2022-07-21 21:58:04 +02:00
38ae5d095c add windows ssse3,sse4_1,sse4_2 detection for non avx path (#251)
* add windows ssse3,sse4_1,sse4_2 detection for non avx path

* remove special WESTMERE case

* move windows conditional redefinition to separate header

* fix minor issues
2022-07-21 21:56:50 +02:00
8eb944f55d add comet lake support #248 (#249) 2022-07-13 10:28:34 +02:00
db9ad9fc2c Add not about avx512_4vbmi2 being an alias of avx512_4fmaps 2022-07-12 15:45:51 +00:00
8360923923 Add macros for RISCV features (#244)
Co-authored-by: Michael Roe <michael-roe@users.noreply.github.com>
2022-07-12 11:41:15 +02:00
3c4801d12d Add AMD ZEN 4 uarch and update detection (#243)
* Add AMD ZEN 4 uarch and update detection

* Add tests via cpuid dump
2022-06-17 11:18:05 +02:00
08f2dc115e Added some MIPS features. (#241)
Co-authored-by: Michael Roe <michael-roe@users.noreply.github.com>
2022-06-01 15:58:29 +02:00
8b3f891d9b Added CPU_FEATURES_COMPILED_MIPS_MIPS3D. (#240)
Co-authored-by: Michael Roe <michael-roe@users.noreply.github.com>
2022-05-19 11:57:13 +02:00
b04a9daf71 Update AArch64 features to Linux 5.17. (#237) 2022-04-27 10:26:29 +02:00
1d02169588 Add support for ZHAOXIN CPU (#218) 2022-02-18 16:32:06 +01:00
149916384b [x86] Embed brand_string and mark FillX86BrandString as deprecated (#214) 2022-01-14 17:20:31 +01:00
aa642e573e [NFC] Avoid polluting global scope 2022-01-14 16:06:30 +00:00
5695cc4817 Update uarch detection for Intel processors (#184) 2021-10-29 10:41:50 +02:00
f96d5f74d4 NFC remove reference to libc memory functions 2021-10-28 11:56:57 +00:00
deb2a61b80 New code layout - breaking change in cpu_features_macros.h (#194)
This commit helps with platform code separation (fixes #3). It should also help with the build as we can simply include all `impl_*.c` files regardless of OS / arch.

Note: this patch contains breaking changes in `include/cpu_features_macros.h`
 - `CPU_FEATURES_OS_LINUX_OR_ANDROID` does not exist anymore
 - `CPU_FEATURES_OS_FREEBSD`, `CPU_FEATURES_OS_ANDROID` and `CPU_FEATURES_OS_LINUX` are now mutually exclusive (i.e. `CPU_FEATURES_OS_ANDROID` does not imply `CPU_FEATURES_OS_LINUX`)
 - `CPU_FEATURES_OS_DARWIN` has been renamed into `CPU_FEATURES_OS_MACOS` to be able to target non-Mac Apple products (IOS, TV, WATCH). They are now targetable with `CPU_FEATURES_OS_IPHONE`. This matches Apple naming convention described in [this stackoverflow](https://stackoverflow.com/a/49560690).
2021-10-28 13:52:46 +02:00
0925f6953c Add cache info for new AMD CPUs (0x8000001D) (#171) 2021-10-18 14:14:29 +02:00
f70dc46cd5 Add separator to CpuFeatures_StringView_HasWord (#174) 2021-10-18 12:52:14 +02:00
119943707c Add support for FreeBSD on x86 (#163) 2021-07-02 15:37:03 +02:00
5492c4c561 CPU features for AMD (#165) 2021-06-30 12:38:56 +02:00
b3ef4ef49d Avoid leaking internal headers for ppc (#164) 2021-06-30 11:51:26 +02:00
001faefdc3 fix: Return default value from ‘GetCacheTypeString’ (#162)
The build fails with following message when -Werror
and -Werror=return-type are enabled.

In function ‘GetCacheTypeString’:
	error: control reaches end of non-void function [-Werror=return-type]

Simple fix is to return explicitly communicate to
the compiler that certain block is not reachable.
2021-06-25 10:28:26 +02:00
d35e2f38eb Detect Intel's Multi-Precision Add-Carry Instruction Extensions (#157) 2021-05-21 10:47:32 +02:00
7ed0b0e50e Detect Zen 3 (K19) cpus (#152)
Co-authored-by: natanbc <natanbc@users.noreply.github.com>
2021-02-25 21:47:39 +01:00
e2f6dea65f Update AArch64 features to Linux 5.10 (#149)
Added feature: MTE.
2020-12-15 13:28:53 +01:00
9a8f04b24c [NFC] Generate separate tables via macro (#137)
This is a non functional change, it allows:
 - Getting rid of `unix_features_aggregator`
 - Have a single blob describing the features
 - Fix wrong mocking of `hwcaps`

Downside: abuse of macros makes the code slightly magical and harder to understand.
It think it's still an improvement over the current situation as there's less repetition and less chances to get something wrong.
2020-10-12 09:50:35 +00:00
3cc8f310d9 [NFC] Update copyright from Google Inc. to Google LLC 2020-10-12 08:55:20 +00:00
4795373db2 Fix SSE detection on non-AVX CPUs (#135)
Fixes #4. This is based on #115 with a few modifications:
 - Removed use of __builtin_cpu_supports since it relies on cpuid and doesn't improve on the current situation,
 - Added detection for all of sse, sse2, sse3, ssse3, sse4_1 and sse4_2,
 - Added tests for Atom, Nehalem, and P3 processors,

Thx to @gadoofou87 for providing the original PR.
It also removes the need for #92

* Fix SSE detection on non-AVX CPUs
* Fixes typo
* Mock OSX sysctlbyname in tests
* Also update other tests
* FakeCpu is reset between each tests
* Fix conflicting name on Windows
* Disable pre AVX cpu sse detection tests on Windows
* Guard OS specific code with macros
* Fix missing import for tests
* Fix wrong function prototype
* Fix wrong mocking of P3 on Windows
* Completely guard OS specific parts in x86 tests
* Store DWORD instead unsigned long for x86 tests
2020-10-09 15:20:25 +00:00
22a5362e11 [NFC] clang-format codebase (#134)
* [NFC] clang-format codebase

* revert to 80 char columns at the price of uglier table init

* Specifically disabling clang-format for table initialization
2020-09-23 09:52:20 +00:00
17ffb65117 detect AVX-512 FMA count (#125)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* second FMA features - incomplete and wrong

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* oops: use T/F not 2/1

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* implement SKX lookup

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

* cleanup AVX512 second FMA code

1) remove debug stuff
2) remove ICX - will add details when available

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* fix CPX detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove elses

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove curly braces from single-line conditional bodies

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* apply clang-format

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

Fixes #120
2020-09-22 07:29:46 +00:00
33bd72c1bc detect future Intel AVX/AMX features (#124)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AVX512_BF16 and AVX512_VP2INTERSECT detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* correction for KNM features: s/4VBMI2/4FMAPS/g

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AMX/TMUL bits from 319433-040

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fixes #128
2020-09-21 07:56:26 +00:00
e698327713 add future Intel microarchitectures (#123)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fix #127
2020-09-21 07:54:58 +00:00
73d10ad25b Update features for AArch64 to Linux 5.8 (#122)
This adds the following features: dcpodp, sve2, sveaes, svepmull,
svebitperm, svesha3, svesm4, flagm2, frint, svei8mm, svef32mm,
svef64mm, svebf16, i8mm, bf16, dgh and rng.

With these, all features used by Linux 5.8 on AArch64 is supported.

Fixes #126
2020-09-21 07:50:38 +00:00
3262a55118 Support x86 FMA4 and SSE4A features 2020-03-12 10:58:41 +00:00
ec6354f0f4 Fix case in CPU_FEATURES_COMPILED_X86_AVX2 (Fix #102) 2020-01-29 11:00:11 +01:00
a6d219bed7 Fixes #102 - wrong macros 2020-01-29 11:00:11 +01:00
3d71a964f5 Use a getter function to avoid manual work for future to-be-added cpu features 2020-01-06 16:24:10 +01:00
73a121b1ae Differentiate between different Lake uarch 2020-01-06 16:23:29 +01:00
d835b4958c Update features for AArch64.
Add all missing features up to Linux v5.0.

Features added: evtstrm, atomics, fphp, asimdhp, cpuid, asimdrdm,
jscvt, fcma, lrcpc, dcpop, sha3, sm3, sm4, asimddp, sha512, sve,
asimdfhm, dit, uscat, ilrcpc, flagm, ssbs, sb, paca, pacg.
2019-10-11 11:02:00 +02:00
653d581e03 Add support for leaf2 and leaf4 on Intel's x86 arch (#80)
* Add support for leaf4 on Intel's x86 arch
* Update cpuinfo_x86.h
* Fix typo
* Force compiler to use C99
* Add Intel x86 leaf2 support
* Fixes after review
* Fix review comments
2019-07-02 16:52:25 +02:00
bfd109b687 Completed all missing ARM hwcaps. (#79) 2019-06-26 12:56:52 +02:00
bfb4cf99cc Add CpuIdEx function to pass inputs in ecx register (required for E.g. leaf4) (#77) 2019-06-21 14:13:29 +02:00
3ee4a9e801 Support x86 DCA and SS features (#76)
* Add dca and ss features
* Remove trailing white spaces
2019-06-19 15:06:05 +02:00