In the latest pciutils(v3.13.0), it supports accessing pci registers
by ecam. This patch uses libpci version check to decide whether
flashrom calls libpci and use 0xcf8/0xcfc or ecam to access pci
registers.
BUG=b:359813524
TEST=with libpci >= 3.13.0, flashrom is working with ECAM access
Change-Id: I4549f87c8b01da0a1d3d8ce0b3b75c1f5fa2cbab
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Old wiki website is retired and so is print_wiki.c
Change-Id: I9990add27f7fdddc23ddd1f33306566ce7548417
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
GD25LB512MF: 1.8V 512Mbit shipped with Quad enabled.
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20231213/DS-01012-GD25LB512MF-Rev1.0.pdf
GD25LR512MF: all GD25LB512MF features + RPMC feature
The datasheet is identical with GD25LB512MF for the NOR flash side.
Tested both models on ch347 with erase, read, write, and protection.
Change-Id: I6a0061a43af5966c93c95645b51a640c00f3d829
Signed-off-by: Victor Lim <vlim@gigadevice.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83899
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We used to have two code paths for erase and write, so we had
{erase|write}_by_layout in two variants: *_new and *_legacy.
Now that legacy is removed, *_new can be renamed without *_new
suffix.
Change-Id: Ib21bf29e1993c4fc0516e76fde2ad283eedb50d2
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aarya <aarya.chaumal@gmail.com>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Current code path for erase and write has been enabled in the tree
since May 2023, which is more than 1 year ago (15 months ago),
and legacy path has been disabled since the same time.
Current logic has been officially released in v1.4.0 in July 2024.
Change-Id: I08fd686fecf6a5313eea2d66b368661c664f4800
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aarya <aarya.chaumal@gmail.com>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
As was described in the version 1.4 release notes, this deletes the
Makefile and supporting elements leaving Meson as the only supported
buildsystem.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Ib3cf22cf636ef9b70527b734ffa34aead2a74edd
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
added GD25LF256F on flashchips.c
added GIGADEVICE_GD25LF256F=0x6319 on flashchip.h
GD25LF256F is a higher performance 1.8V 256Mbit SPI flash
I have tested on CH347 with erase, program, read, protection.
Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26
Signed-off-by: Victor <vlim@gigadevice.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This document is converted from Technology page on wiki
https://wiki.flashrom.org/Technology
Change-Id: I93107d6b5530c301dd90f7177758632d9d1810eb
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83584
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The page on wiki is here:
https://wiki.flashrom.org/ISP
Change-Id: If4752f0f02ae973b3d832f42166de643d95c9f97
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
The wiki is moving around, and the URLs are probably not final. Until
the download locations can be nailed down to their final location, tell
curl to follow HTTP redirects.
Change-Id: I52f1c786a376f5c7394fa5bffc689e58f8691c75
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
These programmers have a little information about them on wiki.
It's too little info to create a dedicated page for each
programmer, however info can go to the manpage.
For reference, wiki pages are the following:
https://wiki.flashrom.org/NIC3Comhttps://wiki.flashrom.org/Gfxnvidiahttps://wiki.flashrom.org/Supported_programmers (search for the
programmers in the table).
Change-Id: Id2a2aefc6a3c8348fdaa4498aaa704fd2da7602f
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83467
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MX25U25645G has been tested by ch341a programmer : read, write,
erase and wp.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.
MX25U25645G datasheet is available at the following URL:
https://www.mxic.com.tw/Lists/Datasheet/Attachments/8738/MX25U25645G,%201.8V,%20256Mb,%20v1.4.pdf
Change-Id: I8641f36e1909274629690fc243be46281a21360d
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Feature bits are too complicated to understand if we only read the
codes/datasheets. Add a new section in how_to_add_new_chip to add more
details about each feature bits.
Add the detailed explanation for WRSR handling first. If this new
section looks good, I'll try to add some more sections in further
commits.
BUG=b:345154585
TEST=meson compile -C builddir and view the doc.
Change-Id: I34c20933a375380c8702f79ac637595cd3466000
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Remove symbol names from the map that do not exist in the code.
https://bugs.gentoo.org/928955
Change-Id: I30bab842d9cbd2daaa9902fd3223f47145cb0e7f
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83261
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
This change extends the ich_descriptors_tool to recognize and process
descriptors for Intel's upcoming Panther Lake SoC.
BUG=b:347669091
TEST=ich_descriptors_tool is able to detect "panther" chipset and show
below information:
> ./util/ich_descriptors_tool/ich_descriptors_tool
Need the file name of a descriptor image to read from.
usage: './util/ich_descriptors_tool/ich_descriptors_tool -f
<image file name> [-c <chipset name>] [-d]'
...
...
To also print the data stored in the descriptor straps you have to
indicate the chipset series with the '-c' parameter and one of the
possible arguments:
- "ich8",
- "ich9",
- "ich10",
- "apollo" for Intel's Apollo Lake SoC.
- "gemini" for Intel's Gemini Lake SoC.
- "jasper" for Intel's Jasper Lake SoC.
- "meteor" for Intel's Meteor Lake SoC.
- "panther" for Intel's Panther Lake SoC.
...
...
- "300" or "cannon" for Intel's 300 series chipsets.
- "400" or "comet" for Intel's 400 series chipsets.
- "500" or "tiger" for Intel's 500 series chipsets.
- "600" or "alder" for Intel's 600 series chipsets.
Change-Id: I17d616d346daca15b43eb294401ac0c672b64c4a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83149
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Recently Android Bionic LibC got sys/io.h. Use this header to access
ioperm(). Use Assembly for I/O, as Bionic does not have inb(), outb(),
etc.
Tested on Android 14 by adding flashrom and pciutils as external repositories, adding Android.bp blueprints (Android specialized build system - Soong), building, running and accessing (read, erase, write) SPI flash on x86 device.
Change-Id: Id80b83c2718679c925ed6ddfe33cbe837eea0429
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83133
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Without this, default value is the first in enum, which is OK. While
in reality, for the chips in the patch block-protection is not
available, so should be NA.
wp test status support was introduced later than the others, so old
chips don't have this field initialised.
Change-Id: I6ed8e04cd215865dc6a7d9415634dedbe3014ab5
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83132
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
