Success report with MX29F001TPC-12 at:
http://flashrom.org/pipermail/flashrom/2011-April/006132.html
Corresponding to flashrom svn r1309.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Remove the array spi_programmer, replace it by dynamic registration
instead. Also initially start with no busses supported, and switch to
the default non-SPI only for the internal programmer.
Also this patch changes the initialization for the buses_supported variable
from "everything-except-SPI" to "nothing". All programmers have to set the
bus type on their own, and this enables register_spi_programmer to just add
the SPI both for on-board SPI interfaces (where the internal programmer
already detected the other bus types), as well as for external programmers
(where we have the default "none").
Corresponding to flashrom svn r1299.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
r1293 introduced a bug which caused probing to loop at the first found
chip.
Corresponding to flashrom svn r1296.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Idwer Vollering <vidwer@gmail.com>
Corresponding to flashrom svn r1295.
Signed-off-by: John Schmerge <jbschmerge@gmail.com> for Devon IT
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Handle board-specific quirks in three phases:
1. Before Super I/O probing (e.g. blacklisting of some Super I/O probes,
or unhiding the Super I/O)
2. Before the laptop enforcement decision (e.g. whitelisting a laptop
for flashing)
3. After chipset enabling (all current board enables)
Implementation note: All entries in board_pciid_enables get an
additional phase parameter. Alternative variants (3 tables instead of 1)
also have their downsides, and I chose table bloat over table
multiplication).
With this patch, it should be possible to whitelist supported laptops
with a matching entry (phase P2) in board_pciid_enables which points to
a function setting laptop_ok=1. (In case DMI is broken, matching might
be a little bit more difficult, but it is still doable.)
Corresponding to flashrom svn r1294.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
This moves 99.5% of the .data section to .rodata (which ends up in .text).
Corresponding to flashrom svn r1293.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reversible MMIO space writes now use rmmio_write*().
Reversible PCI MMIO space writes now use pci_rmmio_write*().
If a MMIO value needs to be queued for restore without writing it,
use rmmio_val*().
MMIO space writes which are one-shot (e.g. communication with some chip)
should continue to use the permanent mmio_write* variants.
Corresponding to flashrom svn r1292.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
David tested it successfully on some NM10/ICH7 platforms which switch
between SPI and LPC targets (x86 BIOS ROM vs. EC firmware ROM).
Acked-by: David Hendricks <dhendrix@google.com>
Corresponding to flashrom svn r1291.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Flashrom currently only supports exactly one Super I/O or Embedded
Controller, and this means quite a few notebooks and a small subset of
desktop/server boards cannot be handled reliably and easily.
Allow detection and initialization of up to 3 Super I/O and/or EC chips.
WARNING! If a Super I/O or EC responds on multiple ports (0x2e and
0x4e), the code will do the wrong thing (namely, initialize the hardware
twice). I have no idea if we should handle such situations, and whether
we should ignore the second chip with identical ID or not. Initializing
the hardware twice for the IT87* family is _not_ a problem, but I don't
know how well IT85* can handle it (and whether IT85* would listen at
more than one port anyway).
Corresponding to flashrom svn r1289.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Thanks to Thomas Schneider for testing on a board with ITE IT87* SPI.
Test report (success) is here: http://paste.flashrom.org/view.php?id=379
Thanks to David Hendricks for testing on a Google Cr-48 laptop with
ITE IT85* EC SPI. Test report (success) is here:
http://www.flashrom.org/pipermail/flashrom/2011-April/006275.html
Acked-by: David Hendricks <dhendrix@google.com>
It is extremely unlikely that a chip not requiring delays in probe does
require them in erase. We observed unreliable erasing with a SST49LF004A
with these delays, so remove them if the are not required.
In review, I got the hint that "probe_jedec goes further by making that
call conditional on nonzero delay". I decided to ignore that. For
internal_delay, the small amount of clock cycles wasted for calling
programmer_delay(0) is negligible compared to LPC cycle times. It might
be an issue for 5 wasted bytes on the serial line in serprog. OTOH,
flash erase is still slow compared to 6*5 bytes on a serial port at
reasonable speed.
Corresponding to flashrom svn r1288.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
As the comment indicates, that function is not a chip erase function
at all, but a function calling a block eraser in a loop. So it adds
no extra value to what we already have in the block_eraser
infrastructure.
Furthermore, that function assumes a uniform sector size layout, but
is referenced from flash chip with non-uniform sector size layout, which
is just wrong.
Corresponding to flashrom svn r1287.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Use 16-bit values for bit masks in 16-bit registers.
Check for SPI Cycle In Progress and wait up to 60 ms.
Do not touch reserved bits.
Reduce SPI cycle timeout from 60 s to 60 ms.
Clear transaction errors caused by our own SPI accesses.
Add better debugging in case the hardware misbehaves.
Corresponding to flashrom svn r1281.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Fix various minor compile issues (eg. include necessary standard headers)
- Fix compilation of libpayload code paths
- Provide libpayload support in Makefile
- Add make target "libflashrom.a" which links non-CLI code to static
library
Corresponding to flashrom svn r1280.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Tested-with-DOS-crosscompiler-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Fix a few typos.
Change the EC memory region mapping name.
Drop unused function parameter.
Use mmio_writeb()/mmio_readb() to get reliable access to volatile memory
locations instead of plain pointer access which is optimized away by gcc.
Use own it85_* SPI high-level chip read/write functions instead of
relying on unrelated ICH functions.
Corresponding to flashrom svn r1279.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
David writes:
I applied the patch against the Chromium OS branch and
successfully tested read and write operations on a Cr48.
Acked-by: David Hendricks <dhendrix@google.com>
Fix compilation if everything except CONFIG_SATAMV is no.
Do not compile in PCI support for wiki printing if no PCI devices are
supported.
Corresponding to flashrom svn r1278.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Simplify pcidev_init by killing the vendorid parameter which was pretty
useless anyway since it was present in the pcidevs parameter as well.
This also allows us to handle multiple programmers with different vendor
IDs in the same driver.
Fix compilation of flashrom with only the nicrealtek driver.
Corresponding to flashrom svn r1274.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Only list the memory controller PCI IDs because the only other subsystem
mentioned is used by network and sound interfaces both of which can be
turned off in BIOS.
Tested on a board rev 1.85.
Corresponding to flashrom svn r1273.
Signed-off-by: Diego Elio Pettenò <flameeyes@gmail.com>
Acked-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Tests were performed with write and verify operations to 4 different
M25PX16 chips with a Dediprog SF100.
Corresponding to flashrom svn r1270.
Signed-off-by: Carl Worth <carl.d.worth@intel.com>
Acked-by: Idwer Vollering <vidwer@gmail.com>
Mark EVGA nForce 780i board as supported.
Full logs are here:
http://www.flashrom.org/pipermail/flashrom/2011-January/005779.html
Corresponding to flashrom svn r1269.
Signed-off-by: Brandon Dowdy <brandonrd7@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Gigabyte is not really helpful with their PCI IDs for us, the subsystem
IDs used just mean "gigabyte northbridge" and "gigabyte southbridge".
We should investigate whether autodetection of this board is causing
interference with other boards.
real version 2: Extend list of PCI IDs for nvidia southbridges.
flashrom -V: http://paste.flashrom.org/view.php?id=326
lspic: http://paste.flashrom.org/view.php?id=328
superiotool: http://paste.flashrom.org/view.php?id=329
Corresponding to flashrom svn r1266.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This code has been deployed and tested to work on the Cr-48.
There are a few caveats, though:
- The boot BIOS straps register must be modified to select LPC. This
can be done with the "select_bbs.sh" script (Install iotools at
http://code.google.com/p/iotools/ before using select_bbs).
- It is very important to disable power management daemons before
running flashrom on this EC. I commented out the brute force method
we use in the Chromium OS branch that disables powerd, since IIRC
Carl-Daniel has a better approach in the works.
- Due to dependencies which may be introduced by the OEM/ODM EC
firmware, the code is not guaranteed to work for anything other than
the Cr-48.
Corresponding to flashrom svn r1263.
Signed-off-by: David Hendricks <dhendrix@google.com>
Carl-Daniel comments:
Code is not hooked up yet because probing needs to be sorted out.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
The patch was developed by Google.
It was tested for IT8500E on a Chrome OS platform and may require
modification depending on ODM/OEM customization and EC firmware version.
This patch is not officially supported by ITE Tech Inc.
Corresponding to flashrom svn r1262.
Signed-off-by: Donald Huang <donald.huang@ite.com.tw>
Signed-off-by: Yung-chieh Lo <yjlou@google.com>
Signed-off-by: David Hendricks <dhendrix@google.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Add more sanity checks for BARs and abort if resources are unreachable.
Undecoded resources are reported, but flashrom will proceed anyway just
in case the BIOS screwed up the configuration.
(The empty CardBus handler is intentional, according to the spec no BARs
in PCI config space are used by CardBus.)
Found while working on a driver for the Angelbird PCIe-based SSD which
has 64-bit capable MEM BARs.
Corresponding to flashrom svn r1261.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
