As was described in the version 1.4 release notes, this deletes the
Makefile and supporting elements leaving Meson as the only supported
buildsystem.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Ib3cf22cf636ef9b70527b734ffa34aead2a74edd
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
added GD25LF256F on flashchips.c
added GIGADEVICE_GD25LF256F=0x6319 on flashchip.h
GD25LF256F is a higher performance 1.8V 256Mbit SPI flash
I have tested on CH347 with erase, program, read, protection.
Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26
Signed-off-by: Victor <vlim@gigadevice.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
This document is converted from Technology page on wiki
https://wiki.flashrom.org/Technology
Change-Id: I93107d6b5530c301dd90f7177758632d9d1810eb
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83584
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The page on wiki is here:
https://wiki.flashrom.org/ISP
Change-Id: If4752f0f02ae973b3d832f42166de643d95c9f97
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
The wiki is moving around, and the URLs are probably not final. Until
the download locations can be nailed down to their final location, tell
curl to follow HTTP redirects.
Change-Id: I52f1c786a376f5c7394fa5bffc689e58f8691c75
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
These programmers have a little information about them on wiki.
It's too little info to create a dedicated page for each
programmer, however info can go to the manpage.
For reference, wiki pages are the following:
https://wiki.flashrom.org/NIC3Comhttps://wiki.flashrom.org/Gfxnvidiahttps://wiki.flashrom.org/Supported_programmers (search for the
programmers in the table).
Change-Id: Id2a2aefc6a3c8348fdaa4498aaa704fd2da7602f
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83467
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MX25U25645G has been tested by ch341a programmer : read, write,
erase and wp.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.
MX25U25645G datasheet is available at the following URL:
https://www.mxic.com.tw/Lists/Datasheet/Attachments/8738/MX25U25645G,%201.8V,%20256Mb,%20v1.4.pdf
Change-Id: I8641f36e1909274629690fc243be46281a21360d
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Feature bits are too complicated to understand if we only read the
codes/datasheets. Add a new section in how_to_add_new_chip to add more
details about each feature bits.
Add the detailed explanation for WRSR handling first. If this new
section looks good, I'll try to add some more sections in further
commits.
BUG=b:345154585
TEST=meson compile -C builddir and view the doc.
Change-Id: I34c20933a375380c8702f79ac637595cd3466000
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Remove symbol names from the map that do not exist in the code.
https://bugs.gentoo.org/928955
Change-Id: I30bab842d9cbd2daaa9902fd3223f47145cb0e7f
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83261
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
This change extends the ich_descriptors_tool to recognize and process
descriptors for Intel's upcoming Panther Lake SoC.
BUG=b:347669091
TEST=ich_descriptors_tool is able to detect "panther" chipset and show
below information:
> ./util/ich_descriptors_tool/ich_descriptors_tool
Need the file name of a descriptor image to read from.
usage: './util/ich_descriptors_tool/ich_descriptors_tool -f
<image file name> [-c <chipset name>] [-d]'
...
...
To also print the data stored in the descriptor straps you have to
indicate the chipset series with the '-c' parameter and one of the
possible arguments:
- "ich8",
- "ich9",
- "ich10",
- "apollo" for Intel's Apollo Lake SoC.
- "gemini" for Intel's Gemini Lake SoC.
- "jasper" for Intel's Jasper Lake SoC.
- "meteor" for Intel's Meteor Lake SoC.
- "panther" for Intel's Panther Lake SoC.
...
...
- "300" or "cannon" for Intel's 300 series chipsets.
- "400" or "comet" for Intel's 400 series chipsets.
- "500" or "tiger" for Intel's 500 series chipsets.
- "600" or "alder" for Intel's 600 series chipsets.
Change-Id: I17d616d346daca15b43eb294401ac0c672b64c4a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83149
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Recently Android Bionic LibC got sys/io.h. Use this header to access
ioperm(). Use Assembly for I/O, as Bionic does not have inb(), outb(),
etc.
Tested on Android 14 by adding flashrom and pciutils as external repositories, adding Android.bp blueprints (Android specialized build system - Soong), building, running and accessing (read, erase, write) SPI flash on x86 device.
Change-Id: Id80b83c2718679c925ed6ddfe33cbe837eea0429
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83133
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Without this, default value is the first in enum, which is OK. While
in reality, for the chips in the patch block-protection is not
available, so should be NA.
wp test status support was introduced later than the others, so old
chips don't have this field initialised.
Change-Id: I6ed8e04cd215865dc6a7d9415634dedbe3014ab5
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83132
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This also expands the column for test status by 1 more char, since
now maximum status is longer, PREWB vs PREW.
print.c runs when command line option `flashrom -L` is invoked.
Change-Id: If697fe3ba93dbe34bb8f7a9a4b1686fdb8b3ee58
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83131
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit hash 85b977151b8f57 (ichspi.c: Add support for region 9 and
beyond in Meteor Lake) moved the Intel Meteor Lake macro in
programmer.h, causing flashrom to display an incorrect chipset name
for Meteor Lake platforms.
This patch updates the corresponding chipset_names index to resolve this
issue.
TEST=Verified correct chipset name in flashrom output for Meteor Lake
chipset (google/rex0 board).
Change-Id: Ic09cf0474c980369bcbf90924d45f697bc1b0a0d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83143
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current numbers are taken from the output of `flashrom -L` command.
Intro page still has a room for improvement, but as a first step the
numbers need to be updated. In future, maybe there is a way to update
the numbers less manually.
Change-Id: I7531521955dcf01348ed2ba9c54316b32b9cd925
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83130
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds two lines at the very end of the section with supported
deviced per programmer. At the moment of this patch, numbers are:
Supported USB devices, total 30
Supported PCI devices, total 94
All other sections print total numbers, this was only one missing.
Change-Id: Ie011db3985172d05f5160d1cb1cc39a4422a5750
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83129
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
