The MX25R2035F has been tested by ch341a programmer : read, write,
erase and wp.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.
MX25R2035F datasheet is available at the following URL:
https://www.macronix.com/Lists/Datasheet/Attachments/8696/MX25R2035F,%20Wide%20Range,%202Mb,%20v1.6.pdf
Change-Id: I00e76ef942976e3e102cf71fe695c6287b392b64
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
The MX25L1633E has been tested by ch341a programmer : read, write,
erase and wp.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.
MX25L1633E datasheet is available at the following URL:
https://www.macronix.com/Lists/Datasheet/Attachments/8617/MX25L1633E,%203V,%2016Mb,%20v1.8.pdf
Change-Id: I63ee0182ad6e62b7408136285aa0e927d53f7bc8
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
The MX25L3239E has been tested by ch341a programmer : read, write,
erase and wp.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.
MX25L3239E datasheet is available at the following URL:
https://www.mxic.com.tw/Lists/Datasheet/Attachments/8613/MX25L3239E,%203V,%2032Mb,%20v1.3.pdf
Change-Id: Ic7a848028fe937deb1bf83ef2a9dddf1330334b6
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
The MX25R8035F has been tested by ch341a programmer : read, write,
erase and wp.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.
MX25R8035F datasheet is available at the following URL:
https://www.macronix.com/Lists/Datasheet/Attachments/8749/MX25R8035F,%20Wide%20Range,%208Mb,%20v1.6.pdf
Change-Id: Iec244ffc29278c1f8c3ae47d17af2c4fe5fbe498
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81837
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MX25L12850F has been tested by ch341a programmer : read, write,
erase and wp.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.
MX25L12850F datasheet is available at the following URL:
https://www.macronix.com/Lists/Datasheet/Attachments/8632/MX25L12850F,%203V,%20128Mb,%20v1.0.pdf
Change-Id: I71ac70d273904f94d015401f9d8df587084efad0
Signed-off-by: DanielZhang <danielzhang@mxic.com.cn>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81350
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Q127C and Q128C are not the same. Q127C doesn't support QPI but Q128C
does. So we need to split the existing GD25Q127C/GD25Q128C into two
separated entries. We also introduce the new flashchip Q128E and merge
it into Q127C.
Datasheets:
Q128E: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00480-GD25Q128E-Rev1.2.pdf
Q127C: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00220-GD25Q127C-Rev2.3.pdf
Q128C: https://www.endrich.com/sixcms/media.php/2/GD25Q128C-Rev2.pdf
Q128E and Q127C/Q128C have compatible main functions, their differences
are:
* Q128E uses 55 nm process, while Q127C/Q128C use 65nm
* Q128E/Q127C does not support QPI
* Q128E/Q127C have OTP: 3072B, while Q128C are 1536B
* Q128E's fast read clock frequency is 133MHz, while Q127C/Q128C are
104MHZ
So we decided to merge Q128E into Q127C.
We also tested that Q128E could pass flashrom_tester while probing it as
127C/128C, so the main functionalities are compatible.
Change the chip name from GD25Q127C/GD25Q128C to two entries
GD25Q127C/GD25Q128E and GD25Q128C to make it more accurate.
Chip revision history:
- The 'GD25Q127C/GD25Q128C' definition was added in
`commit e0c7abf219b81ad049d09a4671ebc9196153d308` as 'GD25Q128C' and
later renamed to 'GD25Q127C/GD25Q128C'
BUG=b:304863141, b:293545382
BRANCH=none
TEST=flashrom_tester with flashrom binary could pass with Q128E,
which contains probe, read, write, erase, and write protect
Signed-off-by: Hsuan Ting Chen <roccochen@google.com>
Change-Id: I3300671b1cf74b3ea0469b9c5a833489ab4914f5
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
XM25QH80B has the same ID as M45PE80, but has more features.
Tested with CH341A.
Change-Id: Ib51225426d8d1a381d45af3574e5ba2bf02837aa
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63516
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on https://github.com/flashrom/flashrom/pull/204
squashed with fixes of IS25WQ040 size: it is 4Mbits, not 4MBytes, see
https://www.issi.com/WW/pdf/25WQ020-040.pdf
Tested read, write and erase with ft2232_spi-based "Tigard" programmer.
Change-Id: I072c6b94d7931637d1c2721c3316205f2d57320e
Signed-off-by: Roman Stingler <roman.stingler@gmail.com>
Signed-off-by: Vasily Galkin <galkin-vv@ya.ru>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58179
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested using the linux_spi programmer on a Raspberry Pi.
Datasheet:
https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L3255E.pdf
Signed-off-by: Joseph C. Lehner <joseph.c.lehner@gmail.com>
Change-Id: I65968771e22e6b823d2d6192c33f5b0cba25d5b9
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/57410
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested: read, write and erase.
Chip (and datasheet) have recenty been removed from XMC's website
but can still be retrieved through web archive:
https://web.archive.org/web/20221122191724/https://www.semiee.com/file/XMC/XMC-XM25QH128A.pdf
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Change-Id: Iced40403c6694a55fd648ea2785cdcba21712234
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/69309
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
I took the original patch from Ondrej Hennel [1] and applied the
requested changes. Reading, erasing and writing works.
[1] https://patchwork.ozlabs.org/project/flashrom/list/?series=261647
Change-Id: Iffd7c4284d4d96b30a94f5dee882b5403fdfc183
Signed-off-by: Mario Kicherer <dev@kicherer.org>
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/68295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested read/write/erase/probe operations with a ch341a_spi programmer.
Datasheet is available at https://www.mouser.de/datasheet/2/590/DS-AT25DF011_032-1098683.pdf
Signed-off-by: Hanno Heinrichs <hanno.heinrichs@rwth-aachen.de>
Change-Id: I5a2141f1380e864c843d6a3008fdb02dc1b75131
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51048
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
See https://www.mxic.com.tw/Lists/Datasheet/Attachments/8662/MX25V1635F,%202.5V,%2016Mb,%20v1.4.pdf .
I've tested this patch with the MX25V1635F I have here, using serprog
and ftdi by (re)writing a few images to the flash and seeing if changes
were stored correctly. This also included erasing and rewriting the
memory with completely different data, so erase is tested, too.
Change-Id: I58ddaaa96ef410d50dde3aaa20376c5bbf0f370b
Signed-off-by: PoroCYon <p@pcy.be>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/73824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
See https://www.macronix.com/Lists/Datasheet/Attachments/8405/MX25V8035F,%202.5V,%208Mb,%20v1.0.pdf .
I've only tested this patch with the MX25V1635F I have here, though
other chips in the series exist as well. Tested using serprog and ftdi
by writing a few images to the flash and seeing if changes were stored
correctly.
Change-Id: Ic5be2da4cfa2a2ff044a519bb6f367f21c15e4b8
Signed-off-by: PoroCYon <p@pcy.be>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/73823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
See https://www.macronix.com/Lists/Datasheet/Attachments/8670/MX25V4035F,%202.5V,%204Mb,%20v1.2.pdf .
I've only tested this patch with the MX25V1635F I have here, though
other chips in the series exist as well. Tested using serprog and ftdi
by writing a few images to the flash and seeing if changes were stored
correctly.
Change-Id: I8b26926c354b840ca7b14b4c5cb000e3c02f5137
Signed-off-by: PoroCYon <p@pcy.be>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/73582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
These chips seem to be rather regular, supporting 2.7V..3.6V, the
common erase block sizes 4KiB, 32KiB, 64KiB and the usual block-
protection bits.
Status/configuration register naming differs from other vendors,
though. These chips have 2 status registers plus 3 configuration
registers. Configuration registers 1 & 2 match status registers
2 & 3 of what we are used from other vendors. Read opcodes match
too, however writes are always done through the WRSR instruction
which can write up to 4 bytes (SR1, CR1, CR2, CR3).
S25FL256L supports native 4BA commands and entering a 4BA mode.
However, it uses an unusual opcode (0x53) for the 32KiB 4BA block
erase.
Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: I356df6649f29e50879a4da4183f1164a81cb0a09
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64747
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Winbond W25Q512NW-IM chip ID and specs to flashrom.
BUG=b:200173901
BRANCH=none
TEST=flash W25Q512NW-IM using CCD.
Original-Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65
Original-Signed-off-by: Atul Dhudase <adhudase@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/3171890
Original-Reviewed-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Shelley Chen <shchen@chromium.org>
Original-Commit-Queue: Shelley Chen <shchen@chromium.org>
(cherry picked from commit facb282e8939b8e4ad15d2478ed9ef86d98aed61)
Note: this commit was cherry-picked from the cros tree but
includes corrections to errors in the original commit's 4BA
feature flags that were spotted by Angel Pons
Change-Id: I9debeda01d77444a5ebe9808ff80a337f320ef65
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Move all header files to the new `include` directory.
Adapt include directives and build systems to the new directory.
Change-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
