Move hwaccess.h #include from flash.h to individual drivers.
libflashrom users need flash.h, but they do not care about hwaccess.h
and should not see its definitions because they may conflict with
other hardware access functions and #defines used by the libflashrom
user.
Corresponding to flashrom svn r1549.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Handle PCI Device ID 0x0360 for MCP55 ISA bridge GPIO as well.
Tested-by: Stefan A. Scholtz
Corresponding to flashrom svn r1547.
Signed-off-by: Joshua Roys <roysjosh@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Add ITE IT8707F/IT8710F detection.
Note that we autodetect those chips, but we don't handle their flash
translation features automatically yet.
Corresponding to flashrom svn r1533.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Not hooked up to the superio detection framework yet.
Corresponding to flashrom svn r1529.
Signed-off-by: David Borg <borg.db@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
These are used in ASUS RS120-E5/PA2 servers.
GPIO pin discovered, patch prepared and
Tested-by: Geoffrey McRae
Corresponding to flashrom svn r1526.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Primary IDs SMBus controller, secondary IDs MCH.
The reverse engineering was done by Michael Karcher.
Андрей Тимираев <dark_prof@mail.ru> reported the problem, but did not
reply (yet) to our propsed fix.
Corresponding to flashrom svn r1516.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
The vendor enable does some other funky stuff with MTRRs/MSRs, SMIs,
cache and legacy ISA address forward twiddling. I would only use
this patch to read and verify the existing contents, just to be safe.
The PCI IDs of the onboard devices do contain no subsystem IDs at all.
Probing and reading was
Tested-by: Ville Skyttä <ville.skytta@iki.fi>
See http://www.flashrom.org/pipermail/flashrom/2010-October/005256.html
Corresponding to flashrom svn r1501.
Signed-off-by: Joshua Roys <roysjosh@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This patch adds a generic phase 2 board enable that does nothing but set
is_laptop to 0 to circumvent an erroneous laptop detection due to ambigous
DMI chassis information.
Corresponding to flashrom svn r1487.
Signed-off-by: Ingo Feldschmid <ifel@msc-ge.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Typical AWARD enable structure with an ICH GPIO board enable.
This board seems also to be known as D2544-B1.
Success report:
http://www.flashrom.org/pipermail/flashrom/2012-January/008590.html
Corresponding to flashrom svn r1486.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Oliver Rath <rath@mglug.de>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
NOTE:
The --list-supported-wiki output changed to use -p internal:mainboard=
instead of -m
The --list-supported output changed the heading of the mainboard list
from
Vendor Board Status Required option
to
Vendor Board Status Required value for
-p internal:mainboard=
Fix lb_vendor_dev_from_string() not to write to the supplied string.
Corresponding to flashrom svn r1483.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
The reverse engineering was done by Joshua. The actual patch was
fabricated by Paul with some polishing by Stefan.
Success log:
http://www.flashrom.org/pipermail/flashrom/2011-November/008257.html
Corresponding to flashrom svn r1468.
Signed-off-by: Joshua Roys <roysjosh at gmail.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
The reverse engineering was done by Joshua. The actual patch was
fabricated by Stefan.
Request:
http://www.flashrom.org/pipermail/flashrom/2011-November/008241.html
Success report:
http://paste.flashrom.org/view.php?id=914
Corresponding to flashrom svn r1467.
Signed-off-by: Joshua Roys <roysjosh@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Mugendai <mugendai42@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This looks suspiciously like intel_ich_gpio_set.
Based on that, add board enables for the ASUS P5N-D and P5N-E SLI.
This was tested by Guillaume Poirier-Morency on a P5N-D:
http://www.flashrom.org/pipermail/flashrom/2011-August/007706.html
Corresponding to flashrom svn r1466.
Signed-off-by: Joshua Roys <roysjosh@gmail.com>
Small changes were also contributed and
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
All programmers are now calling programmer registration functions and
direct manipulations of buses_supported are not needed/possible anymore.
Note: Programmers without parallel/LPC/FWH chip support should not call
register_par_programmer().
Additional fixes:
Set max_rom_decode.parallel for drkaiser.
Remove abuse of programmer_map_flash_region in it85spi.
Annotate several FIXMEs in it85spi.
Corresponding to flashrom svn r1463.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Changes related to P5GD1 variants:
- Reorder "P5GD1 Pro" in print.c and include a DMI patter to its board enable
- Add an untested "P5GD1(-VM)" board enable and add an entry to print.c
- Add P5GD1-VM/S variant as reported by "Limer"
Changes related to P5GD(2/C) variants:
- Fix the name of "P5GDC-V Deluxe" board enable and add a DMI pattern and
print.c entry. NB: there is no "P5GDC-V" board.
- Add a generic match for P5GD(2/C)* boards with a not tested tag.
This are the potential targets for this according to the asus ftp:
ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/
Unsupported variants of the P5GD2:
P5GD2, P5GD2 Deluxe, P5GD2 Pro, P5GD2-X
(P5GD2 Premium is already tested)
(there seems to be also a P5GD2-TVM/GB/SI in the wild, which is not known to
asus :)
Unsupported variants of the P5GDC:
P5GDC Pro, P5GDC-MX
(P5GDC Deluxe and P5GDC-V Deluxe are already tested)
References:
P5GD1 PRO (dmi "P5GD1 PRO")
smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, *0x814e*
http://www.coreboot.org/pipermail/flashrom/2010-August/004539.html
P5GD1 (dmi "P5GD1")
The non-pro version seems to match the pro pci pattern, but could be
distinguished by the SATA ID of 1043:2604 vs. 1043:2601:
https://launchpadlibrarian.net/62167576/Lspci.txt
or a DMI pattern of course.
P5GD1-VM (dmi "P5GD1-VM")
This does also match the current PCI IDs.
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/465379
- P5GD2 Premium (dmi "P5GD2-Premium")
smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d
http://www.flashrom.org/pipermail/flashrom/2010-August/004555.html
- P5GDC-V Deluxe (dmi "P5GDC-V")
smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d
http://www.flashrom.org/pipermail/flashrom/2010-September/004939.html
- P5GDC Deluxe (dmi "P5GDC")
smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d
http://www.flashrom.org/pipermail/flashrom/2010-September/004684.html
- P5GDC Pro, P5GDC-MX, P5GD2-X, P5GD2 Pro, P5GD2
no useful logs found
- P5GD2-Deluxe (dmi "P5GD2-Deluxe")
smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d
https://bugs.launchpad.net/ubuntu/+source/foomatic-filters/+bug/572514
- P5GD2-TVM/GB/SI (dmi "P5GD2-TVM/GB/SI")
smbus: 0x8086, 0x266a, 0x1043, 0x266a; audio: 0x8086, 0x2668, 0x1043, *0x81a7*
https://bugs.launchpad.net/ubuntu/+source/linux/+bug/462500
Corresponding to flashrom svn r1457.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
and due to the tremendous interest... ;)
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
I disassembled the write enable and the write disable functions from
the Award BIOS image and reconstructed C code to understand for
myself what happens. For details see:
http://www.flashrom.org/pipermail/flashrom/2011-October/008033.html
I compared the download pages of both, abit AV8 and abit AV8-3rd Eye,
and the BIOS downloads are the same. So it's save to assume that this
board enable works on both versions. Tested on AV8.
Corresponding to flashrom svn r1455.
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Based on the REing of Michael Karcher and a good guess of Idwer Vollering.
Corresponding to flashrom svn r1419.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Leon Zhang <leoncamel at gmail.com>
http://www.coreboot.org/pipermail/flashrom/2010-August/004500.html
Tested-by: medhi <nefkongo@hotmail.com>
http://paste.flashrom.org/view.php?id=779
Acked-by: Idwer Vollering <vidwer@gmail.com>
- Mixing uninitialized and initialized local variables leads to
confusion.
- ft2232_spi error cases should have gotten some error handling, and
that's the reason the curly braces were there.
- Fixing typos/wording in some places would have been nice given that
those places were touched anyway.
Corresponding to flashrom svn r1413.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
There are numerous other variants of the P5LD2 which vary wildly not only in
PCB layout but also in northbridges used, number of PCI, PCI-E and DIMM slots
etc. This one is for the plain P5LD2 without any suffixes.
This patch is essentially a rebased version of Joshua's patch, which was never
tested (user did not reply). I have added additional PCI IDs and the DMI pattern
and also changed the status to NT. An entry in the print.c table was also added.
http://www.flashrom.org/pipermail/flashrom/2010-October/005080.html
Corresponding to flashrom svn r1410.
Signed-off-by: Joshua Roys <roysjosh@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
It is based on Joshua Roys' RE.
http://www.flashrom.org/pipermail/flashrom/2011-August/007504.html
Corresponding to flashrom svn r1408.
Tested-by: Márton Miklós
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
- retag it as OK (tested by Jonathan Kollasch when he wrote it)
http://patchwork.coreboot.org/patch/2106/
- add a line with identical pci ids but a different DMI pattern, so that EP-9NPA7I
is also matched. combining multiple boards in one line is problematic due to
print.c's detection of board enables - so dont bother for now.
http://www.flashrom.org/pipermail/flashrom/2011-June/006878.html
See previous commit for additional information.
Corresponding to flashrom svn r1406.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Also, indentation fixes, e.g. due to conversion to msg_*, use ARRAY_SIZE
where possible, wrap overly long line, etc.
Compile-tested. There should be no functional changes.
Corresponding to flashrom svn r1397.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
It's shorter to type, and we have less problems with the 80 column limit.
Corresponding to flashrom svn r1396.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
P5N-E SLI, EP-8NPA7I and EP-9NPA7I all need at least this patch:
http://patchwork.coreboot.org/patch/2125/
the P5N-E also needs a board enable:
http://patchwork.coreboot.org/patch/3298/
mark the boards as not working until those are merged.
Corresponding to flashrom svn r1382.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
http://patchwork.coreboot.org/patch/2893/
lspci: http://paste.flashrom.org/view.php?id=494
only writing a backup file was tested, so mark it as untested.
Corresponding to flashrom svn r1368.
Signed-off-by: Joshua Roys <roysjosh@gmail.com>
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested reading, writing and verification, all worked fine.
Corresponding to flashrom svn r1346.
Signed-off-by: Pawel Rozanski <rozie@poczta.onet.pl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Tested-by: Melroy van den Berg
http://www.flashrom.org/pipermail/flashrom/2010-December/005642.html
Corresponding to flashrom svn r1327.
Based on reverse engineering by Michael Karcher.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Idwer Vollering <vidwer@gmail.com>
Handle board-specific quirks in three phases:
1. Before Super I/O probing (e.g. blacklisting of some Super I/O probes,
or unhiding the Super I/O)
2. Before the laptop enforcement decision (e.g. whitelisting a laptop
for flashing)
3. After chipset enabling (all current board enables)
Implementation note: All entries in board_pciid_enables get an
additional phase parameter. Alternative variants (3 tables instead of 1)
also have their downsides, and I chose table bloat over table
multiplication).
With this patch, it should be possible to whitelist supported laptops
with a matching entry (phase P2) in board_pciid_enables which points to
a function setting laptop_ok=1. (In case DMI is broken, matching might
be a little bit more difficult, but it is still doable.)
Corresponding to flashrom svn r1294.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Flashrom currently only supports exactly one Super I/O or Embedded
Controller, and this means quite a few notebooks and a small subset of
desktop/server boards cannot be handled reliably and easily.
Allow detection and initialization of up to 3 Super I/O and/or EC chips.
WARNING! If a Super I/O or EC responds on multiple ports (0x2e and
0x4e), the code will do the wrong thing (namely, initialize the hardware
twice). I have no idea if we should handle such situations, and whether
we should ignore the second chip with identical ID or not. Initializing
the hardware twice for the IT87* family is _not_ a problem, but I don't
know how well IT85* can handle it (and whether IT85* would listen at
more than one port anyway).
Corresponding to flashrom svn r1289.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Thanks to Thomas Schneider for testing on a board with ITE IT87* SPI.
Test report (success) is here: http://paste.flashrom.org/view.php?id=379
Thanks to David Hendricks for testing on a Google Cr-48 laptop with
ITE IT85* EC SPI. Test report (success) is here:
http://www.flashrom.org/pipermail/flashrom/2011-April/006275.html
Acked-by: David Hendricks <dhendrix@google.com>
Only list the memory controller PCI IDs because the only other subsystem
mentioned is used by network and sound interfaces both of which can be
turned off in BIOS.
Tested on a board rev 1.85.
Corresponding to flashrom svn r1273.
Signed-off-by: Diego Elio Pettenò <flameeyes@gmail.com>
Acked-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
